mlxsw: reg: Add cwtp & cwtpm registers
This patch adds 2 new registers: - Congestion WRED ECN TClass Profile Register [CWTP] - Congestion WRED ECN TClass and Pool Mapping Register [CWTPM] These registers would later be needed to offload RED-related functionality to the HW. Signed-off-by: Yuval Mintz <yuvalm@mellanox.com> Signed-off-by: Nogah Frankel <nogahf@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Nogah Frankel
David S. Miller
parent
8521db4c7e
commit
ad53fa06c1
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@ -1758,6 +1758,191 @@ static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
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}
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}
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/* CWTP - Congetion WRED ECN TClass Profile
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* ----------------------------------------
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* Configures the profiles for queues of egress port and traffic class
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*/
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#define MLXSW_REG_CWTP_ID 0x2802
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#define MLXSW_REG_CWTP_BASE_LEN 0x28
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#define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08
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#define MLXSW_REG_CWTP_LEN 0x40
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MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN);
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/* reg_cwtp_local_port
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* Local port number
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* Not supported for CPU port
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* Access: Index
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*/
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MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8);
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/* reg_cwtp_traffic_class
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* Traffic Class to configure
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* Access: Index
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*/
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MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8);
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/* reg_cwtp_profile_min
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* Minimum Average Queue Size of the profile in cells.
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* Access: RW
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*/
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MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN,
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0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false);
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/* reg_cwtp_profile_percent
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* Percentage of WRED and ECN marking for maximum Average Queue size
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* Range is 0 to 100, units of integer percentage
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* Access: RW
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*/
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MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN,
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24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
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/* reg_cwtp_profile_max
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* Maximum Average Queue size of the profile in cells
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* Access: RW
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*/
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MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN,
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0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
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#define MLXSW_REG_CWTP_MIN_VALUE 64
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#define MLXSW_REG_CWTP_MAX_PROFILE 2
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#define MLXSW_REG_CWTP_DEFAULT_PROFILE 1
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static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port,
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u8 traffic_class)
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{
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int i;
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MLXSW_REG_ZERO(cwtp, payload);
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mlxsw_reg_cwtp_local_port_set(payload, local_port);
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mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class);
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for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) {
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mlxsw_reg_cwtp_profile_min_set(payload, i,
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MLXSW_REG_CWTP_MIN_VALUE);
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mlxsw_reg_cwtp_profile_max_set(payload, i,
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MLXSW_REG_CWTP_MIN_VALUE);
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}
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}
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#define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1)
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static inline void
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mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max,
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u32 probability)
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{
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u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile);
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mlxsw_reg_cwtp_profile_min_set(payload, index, min);
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mlxsw_reg_cwtp_profile_max_set(payload, index, max);
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mlxsw_reg_cwtp_profile_percent_set(payload, index, probability);
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}
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/* CWTPM - Congestion WRED ECN TClass and Pool Mapping
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* ---------------------------------------------------
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* The CWTPM register maps each egress port and traffic class to profile num.
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*/
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#define MLXSW_REG_CWTPM_ID 0x2803
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#define MLXSW_REG_CWTPM_LEN 0x44
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MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN);
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/* reg_cwtpm_local_port
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* Local port number
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* Not supported for CPU port
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* Access: Index
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*/
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MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8);
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/* reg_cwtpm_traffic_class
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* Traffic Class to configure
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* Access: Index
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*/
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MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8);
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/* reg_cwtpm_ew
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* Control enablement of WRED for traffic class:
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* 0 - Disable
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* 1 - Enable
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* Access: RW
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*/
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MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1);
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/* reg_cwtpm_ee
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* Control enablement of ECN for traffic class:
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* 0 - Disable
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* 1 - Enable
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* Access: RW
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*/
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MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1);
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/* reg_cwtpm_tcp_g
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* TCP Green Profile.
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* Index of the profile within {port, traffic class} to use.
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* 0 for disabling both WRED and ECN for this type of traffic.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2);
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/* reg_cwtpm_tcp_y
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* TCP Yellow Profile.
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* Index of the profile within {port, traffic class} to use.
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* 0 for disabling both WRED and ECN for this type of traffic.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2);
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/* reg_cwtpm_tcp_r
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* TCP Red Profile.
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* Index of the profile within {port, traffic class} to use.
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* 0 for disabling both WRED and ECN for this type of traffic.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2);
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/* reg_cwtpm_ntcp_g
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* Non-TCP Green Profile.
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* Index of the profile within {port, traffic class} to use.
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* 0 for disabling both WRED and ECN for this type of traffic.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2);
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/* reg_cwtpm_ntcp_y
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* Non-TCP Yellow Profile.
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* Index of the profile within {port, traffic class} to use.
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* 0 for disabling both WRED and ECN for this type of traffic.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2);
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/* reg_cwtpm_ntcp_r
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* Non-TCP Red Profile.
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* Index of the profile within {port, traffic class} to use.
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* 0 for disabling both WRED and ECN for this type of traffic.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2);
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#define MLXSW_REG_CWTPM_RESET_PROFILE 0
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static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port,
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u8 traffic_class, u8 profile,
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bool wred, bool ecn)
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{
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MLXSW_REG_ZERO(cwtpm, payload);
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mlxsw_reg_cwtpm_local_port_set(payload, local_port);
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mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class);
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mlxsw_reg_cwtpm_ew_set(payload, wred);
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mlxsw_reg_cwtpm_ee_set(payload, ecn);
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mlxsw_reg_cwtpm_tcp_g_set(payload, profile);
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mlxsw_reg_cwtpm_tcp_y_set(payload, profile);
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mlxsw_reg_cwtpm_tcp_r_set(payload, profile);
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mlxsw_reg_cwtpm_ntcp_g_set(payload, profile);
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mlxsw_reg_cwtpm_ntcp_y_set(payload, profile);
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mlxsw_reg_cwtpm_ntcp_r_set(payload, profile);
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}
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/* PPBT - Policy-Engine Port Binding Table
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* ---------------------------------------
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* This register is used for configuration of the Port Binding Table.
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@ -7405,6 +7590,8 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
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MLXSW_REG(svpe),
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MLXSW_REG(sfmr),
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MLXSW_REG(spvmlr),
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MLXSW_REG(cwtp),
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MLXSW_REG(cwtpm),
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MLXSW_REG(ppbt),
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MLXSW_REG(pacl),
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MLXSW_REG(pagt),
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