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ARM: tegra: split setting of CPU reset handler 

Not all Tegra devices can set the CPU reset handler in the same way.
In particular, devices using a TrustZone secure monitor cannot set it
up directly and need to ask the firmware to do it.

This patch separates the act of setting the reset handler from its
preparation, so the former can be implemented in a different way.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Alexandre Courbot 2013-11-24 15:30:50 +09:00 committed by Stephen Warren
parent 1a5de3aeb0
commit ad14ecee4d
1 changed files with 17 additions and 10 deletions
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27
arch/arm/mach-tegra/reset.c
View File

@ -33,26 +33,18 @@
static bool is_enabled; static bool is_enabled;
static void __init tegra_cpu_reset_handler_enable(void) static void __init tegra_cpu_reset_handler_set(const u32 reset_address)
{ {
void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE);
void __iomem *evp_cpu_reset = void __iomem *evp_cpu_reset =
IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100); IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100);
void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE); void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE);
u32 reg; u32 reg;
BUG_ON(is_enabled);
BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE);
memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start,
tegra_cpu_reset_handler_size);
/* /*
* NOTE: This must be the one and only write to the EVP CPU reset * NOTE: This must be the one and only write to the EVP CPU reset
* vector in the entire system. * vector in the entire system.
*/ */
writel(TEGRA_IRAM_RESET_BASE + tegra_cpu_reset_handler_offset, writel(reset_address, evp_cpu_reset);
evp_cpu_reset);
wmb(); wmb();
reg = readl(evp_cpu_reset); reg = readl(evp_cpu_reset);
@ -66,6 +58,21 @@ static void __init tegra_cpu_reset_handler_enable(void)
writel(reg, sb_ctrl); writel(reg, sb_ctrl);
wmb(); wmb();
} }
}
static void __init tegra_cpu_reset_handler_enable(void)
{
void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE);
const u32 reset_address = TEGRA_IRAM_RESET_BASE +
tegra_cpu_reset_handler_offset;
BUG_ON(is_enabled);
BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE);
memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start,
tegra_cpu_reset_handler_size);
tegra_cpu_reset_handler_set(reset_address);
is_enabled = true; is_enabled = true;
} }