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drm/amd/powerplay: add smumgr support for VEGAM (v2) 

The smumgr handles communication between the driver
and the SMU for power management.

v2: fix typo (Alex)

Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Eric Huang 2018-04-11 15:32:58 -05:00 committed by Alex Deucher
parent 4dc1a2d928
commit ac7822b002
4 changed files with 2464 additions and 1 deletions
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6
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
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@ -40,6 +40,7 @@ extern const struct pp_smumgr_func iceland_smu_funcs;
extern const struct pp_smumgr_func tonga_smu_funcs;
extern const struct pp_smumgr_func fiji_smu_funcs;
extern const struct pp_smumgr_func polaris10_smu_funcs;
extern const struct pp_smumgr_func vegam_smu_funcs;
extern const struct pp_smumgr_func vega10_smu_funcs;
extern const struct pp_smumgr_func vega12_smu_funcs;
extern const struct pp_smumgr_func smu10_smu_funcs;
@ -136,6 +137,11 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
polaris_set_asic_special_caps(hwmgr);
hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
break;
case CHIP_VEGAM:
hwmgr->smumgr_funcs = &vegam_smu_funcs;
polaris_set_asic_special_caps(hwmgr);
hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
break;
default:
return -EINVAL;
}

2
drivers/gpu/drm/amd/powerplay/smumgr/Makefile
View File

@ -26,7 +26,7 @@
SMU_MGR = smumgr.o smu8_smumgr.o tonga_smumgr.o fiji_smumgr.o \
polaris10_smumgr.o iceland_smumgr.o \
smu7_smumgr.o vega10_smumgr.o smu10_smumgr.o ci_smumgr.o \
vega12_smumgr.o
vega12_smumgr.o vegam_smumgr.o
AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))

2382
drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c Normal file
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File diff suppressed because it is too large Load Diff

75
drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.h Normal file
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@ -0,0 +1,75 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _VEGAM_SMUMANAGER_H
#define _VEGAM_SMUMANAGER_H
#include <pp_endian.h>
#include "smu75_discrete.h"
#include "smu7_smumgr.h"
#define SMC_RAM_END 0x40000
#define DPMTuning_Uphyst_Shift 0
#define DPMTuning_Downhyst_Shift 8
#define DPMTuning_Activity_Shift 16
#define GraphicsDPMTuning_VEGAM 0x001e6400
#define MemoryDPMTuning_VEGAM 0x000f3c0a
#define SclkDPMTuning_VEGAM 0x002d000a
#define MclkDPMTuning_VEGAM 0x001f100a
struct vegam_pt_defaults {
uint8_t SviLoadLineEn;
uint8_t SviLoadLineVddC;
uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
uint8_t TDC_MAWt;
uint8_t TdcWaterfallCtl;
uint8_t DTEAmbientTempBase;
uint32_t DisplayCac;
uint32_t BAPM_TEMP_GRADIENT;
uint16_t BAPMTI_R[SMU75_DTE_ITERATIONS * SMU75_DTE_SOURCES * SMU75_DTE_SINKS];
uint16_t BAPMTI_RC[SMU75_DTE_ITERATIONS * SMU75_DTE_SOURCES * SMU75_DTE_SINKS];
};
struct vegam_range_table {
uint32_t trans_lower_frequency; /* in 10khz */
uint32_t trans_upper_frequency;
};
struct vegam_smumgr {
struct smu7_smumgr smu7_data;
uint8_t protected_mode;
SMU75_Discrete_DpmTable smc_state_table;
struct SMU75_Discrete_Ulv ulv_setting;
struct SMU75_Discrete_PmFuses power_tune_table;
struct vegam_range_table range_table[NUM_SCLK_RANGE];
const struct vegam_pt_defaults *power_tune_defaults;
uint32_t bif_sclk_table[SMU75_MAX_LEVELS_LINK];
};
#endif