ARM: OMAP2+: cleaned-up DT support of various ECC schemes
OMAP NAND driver support multiple ECC scheme, which can used in different flavours, depending on in-build Hardware engines present on SoC. This patch updates following in DT bindings related to sectionion of ecc-schemes - ti,elm-id: replaces elm_id (maintains backward compatibility) - ti,nand-ecc-opts: selection of h/w or s/w implementation of an ecc-scheme depends on ti,elm-id. (supported values ham1, bch4, and bch8) - maintain backward compatibility to deprecated DT bindings (sw, hw, hw-romcode) Below table shows different flavours of ecc-schemes supported by OMAP devices +---------------------------------------+---------------+---------------+ | ECC scheme |ECC calculation|Error detection| +---------------------------------------+---------------+---------------+ |OMAP_ECC_HAM1_CODE_HW |H/W (GPMC) |S/W | +---------------------------------------+---------------+---------------+ |OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W | |(requires CONFIG_MTD_NAND_ECC_BCH) | | | +---------------------------------------+---------------+---------------+ |OMAP_ECC_BCH8_CODE_HW |H/W (GPMC) |H/W (ELM) | |(requires CONFIG_MTD_NAND_OMAP_BCH && | | | | ti,elm-id in DT) | | | +---------------------------------------+---------------+---------------+ To optimize footprint of omap2-nand driver, selection of some ECC schemes also require enabling following Kconfigs, in addition to setting appropriate DT bindings - Kconfig:CONFIG_MTD_NAND_ECC_BCH error detection done in software - Kconfig:CONFIG_MTD_NAND_OMAP_BCH error detection done by h/w engine Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Felipe Balbi <balbi@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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@ -36,8 +36,12 @@ Optional properties:
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"prefetch-dma" Prefetch enabled sDMA mode
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"prefetch-irq" Prefetch enabled irq mode
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- elm_id: Specifies elm device node. This is required to support BCH
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error correction using ELM module.
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- elm_id: <deprecated> use "ti,elm-id" instead
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- ti,elm-id: Specifies phandle of the ELM devicetree node.
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ELM is an on-chip hardware engine on TI SoC which is used for
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locating ECC errors for BCHx algorithms. SoC devices which have
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ELM hardware engines should specify this device node in .dtsi
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Using ELM for ECC error correction frees some CPU cycles.
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For inline partiton table parsing (optional):
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@ -1341,14 +1341,6 @@ static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
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#ifdef CONFIG_MTD_NAND
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static const char * const nand_ecc_opts[] = {
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[OMAP_ECC_HAMMING_CODE_DEFAULT] = "sw",
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[OMAP_ECC_HAMMING_CODE_HW] = "hw",
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[OMAP_ECC_HAMMING_CODE_HW_ROMCODE] = "hw-romcode",
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[OMAP_ECC_BCH4_CODE_HW] = "bch4",
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[OMAP_ECC_BCH8_CODE_HW] = "bch8",
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};
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static const char * const nand_xfer_types[] = {
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[NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled",
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[NAND_OMAP_POLLED] = "polled",
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@ -1378,13 +1370,41 @@ static int gpmc_probe_nand_child(struct platform_device *pdev,
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gpmc_nand_data->cs = val;
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gpmc_nand_data->of_node = child;
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if (!of_property_read_string(child, "ti,nand-ecc-opt", &s))
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for (val = 0; val < ARRAY_SIZE(nand_ecc_opts); val++)
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if (!strcasecmp(s, nand_ecc_opts[val])) {
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gpmc_nand_data->ecc_opt = val;
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break;
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}
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/* Detect availability of ELM module */
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gpmc_nand_data->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
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if (gpmc_nand_data->elm_of_node == NULL)
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gpmc_nand_data->elm_of_node =
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of_parse_phandle(child, "elm_id", 0);
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if (gpmc_nand_data->elm_of_node == NULL)
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pr_warn("%s: ti,elm-id property not found\n", __func__);
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/* select ecc-scheme for NAND */
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if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
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pr_err("%s: ti,nand-ecc-opt not found\n", __func__);
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return -ENODEV;
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}
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if (!strcmp(s, "ham1") || !strcmp(s, "sw") ||
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!strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
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gpmc_nand_data->ecc_opt =
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OMAP_ECC_HAM1_CODE_HW;
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else if (!strcmp(s, "bch4"))
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if (gpmc_nand_data->elm_of_node)
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gpmc_nand_data->ecc_opt =
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OMAP_ECC_BCH4_CODE_HW;
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else
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gpmc_nand_data->ecc_opt =
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OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
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else if (!strcmp(s, "bch8"))
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if (gpmc_nand_data->elm_of_node)
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gpmc_nand_data->ecc_opt =
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OMAP_ECC_BCH8_CODE_HW;
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else
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gpmc_nand_data->ecc_opt =
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OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
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else
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pr_err("%s: ti,nand-ecc-opt invalid value\n", __func__);
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/* select data transfer mode for NAND controller */
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if (!of_property_read_string(child, "ti,nand-xfer-type", &s))
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for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++)
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if (!strcasecmp(s, nand_xfer_types[val])) {
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@ -28,8 +28,16 @@ enum omap_ecc {
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OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
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/* 1-bit ecc: stored at beginning of spare area as romcode */
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OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */
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OMAP_ECC_BCH4_CODE_HW, /* 4-bit BCH ecc code */
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OMAP_ECC_BCH8_CODE_HW, /* 8-bit BCH ecc code */
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/* 1-bit ECC calculation by GPMC, Error detection by Software */
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OMAP_ECC_HAM1_CODE_HW,
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/* 4-bit ECC calculation by GPMC, Error detection by Software */
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OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
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/* 4-bit ECC calculation by GPMC, Error detection by ELM */
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OMAP_ECC_BCH4_CODE_HW,
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/* 8-bit ECC calculation by GPMC, Error detection by Software */
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OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
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/* 8-bit ECC calculation by GPMC, Error detection by ELM */
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OMAP_ECC_BCH8_CODE_HW,
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};
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struct gpmc_nand_regs {
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@ -63,5 +71,6 @@ struct omap_nand_platform_data {
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/* for passing the partitions */
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struct device_node *of_node;
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struct device_node *elm_of_node;
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};
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#endif
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