Merge branch 'imx/imx6q' into next/soc
Conflicts: Documentation/devicetree/bindings/arm/fsl.txt arch/arm/Kconfig arch/arm/Kconfig.debug arch/arm/plat-mxc/include/mach/common.h
This commit is contained in:
Arnd Bergmann
commit
abc3f126ac
|
|
@ -1,3 +1,6 @@
|
|||
Freescale i.MX Platforms Device Tree Bindings
|
||||
-----------------------------------------------
|
||||
|
||||
i.MX51 Babbage Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,imx51-babbage", "fsl,imx51";
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||||
|
|
@ -17,3 +20,7 @@ Required root node properties:
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|||
i.MX53 Smart Mobile Reference Design Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,imx53-smd", "fsl,imx53";
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||||
|
||||
i.MX6 Quad SABRE Automotive Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
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||||
|
|
|
|||
|
|
@ -793,6 +793,13 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
|||
S: Maintained
|
||||
F: arch/arm/mach-mx5/
|
||||
|
||||
ARM/FREESCALE IMX6
|
||||
M: Shawn Guo <shawn.guo@linaro.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
T: git git://git.linaro.org/people/shawnguo/linux-2.6.git
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||||
F: arch/arm/mach-imx/*imx6*
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||||
|
||||
ARM/GLOMATION GESBC9312SX MACHINE SUPPORT
|
||||
M: Lennert Buytenhek <kernel@wantstofly.org>
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||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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||||
|
|
|
|||
|
|
@ -1435,7 +1435,7 @@ config SMP
|
|||
depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
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||||
MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
|
||||
ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
|
||||
ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK
|
||||
ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q
|
||||
select USE_GENERIC_SMP_HELPERS
|
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select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
|
||||
help
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||||
|
|
|
|||
|
|
@ -135,6 +135,118 @@ choice
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|||
Say Y here if you want the debug print routines to direct
|
||||
their output to the UART on Highbank based devices.
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||||
|
||||
config DEBUG_IMX1_UART
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||||
bool "i.MX1 Debug UART"
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||||
depends on SOC_IMX1
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on i.MX1.
|
||||
|
||||
config DEBUG_IMX23_UART
|
||||
bool "i.MX23 Debug UART"
|
||||
depends on SOC_IMX23
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on i.MX23.
|
||||
|
||||
config DEBUG_IMX25_UART
|
||||
bool "i.MX25 Debug UART"
|
||||
depends on SOC_IMX25
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on i.MX25.
|
||||
|
||||
config DEBUG_IMX21_IMX27_UART
|
||||
bool "i.MX21 and i.MX27 Debug UART"
|
||||
depends on SOC_IMX21 || SOC_IMX27
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on i.MX21 or i.MX27.
|
||||
|
||||
config DEBUG_IMX28_UART
|
||||
bool "i.MX28 Debug UART"
|
||||
depends on SOC_IMX28
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on i.MX28.
|
||||
|
||||
config DEBUG_IMX31_IMX35_UART
|
||||
bool "i.MX31 and i.MX35 Debug UART"
|
||||
depends on SOC_IMX31 || SOC_IMX35
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on i.MX31 or i.MX35.
|
||||
|
||||
config DEBUG_IMX51_UART
|
||||
bool "i.MX51 Debug UART"
|
||||
depends on SOC_IMX51
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on i.MX51.
|
||||
|
||||
config DEBUG_IMX50_IMX53_UART
|
||||
bool "i.MX50 and i.MX53 Debug UART"
|
||||
depends on SOC_IMX50 || SOC_IMX53
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on i.MX50 or i.MX53.
|
||||
|
||||
config DEBUG_IMX6Q_UART
|
||||
bool "i.MX6Q Debug UART"
|
||||
depends on SOC_IMX6Q
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on i.MX6Q.
|
||||
|
||||
config DEBUG_S3C_UART0
|
||||
depends on PLAT_SAMSUNG
|
||||
bool "Use S3C UART 0 for low-level debug"
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to UART 0. The port must have been initialised
|
||||
by the boot-loader before use.
|
||||
|
||||
The uncompressor code port configuration is now handled
|
||||
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
||||
|
||||
config DEBUG_S3C_UART1
|
||||
depends on PLAT_SAMSUNG
|
||||
bool "Use S3C UART 1 for low-level debug"
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to UART 1. The port must have been initialised
|
||||
by the boot-loader before use.
|
||||
|
||||
The uncompressor code port configuration is now handled
|
||||
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
||||
|
||||
config DEBUG_S3C_UART2
|
||||
depends on PLAT_SAMSUNG
|
||||
bool "Use S3C UART 2 for low-level debug"
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to UART 2. The port must have been initialised
|
||||
by the boot-loader before use.
|
||||
|
||||
The uncompressor code port configuration is now handled
|
||||
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
||||
|
||||
config DEBUG_REALVIEW_STD_PORT
|
||||
bool "RealView Default UART"
|
||||
depends on ARCH_REALVIEW
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to the serial port on RealView EB, PB11MP, PBA8
|
||||
and PBX platforms.
|
||||
|
||||
config DEBUG_REALVIEW_PB1176_PORT
|
||||
bool "RealView PB1176 UART"
|
||||
depends on MACH_REALVIEW_PB1176
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to the standard serial port on the RealView
|
||||
PB1176 platform.
|
||||
|
||||
endchoice
|
||||
|
||||
config EARLY_PRINTK
|
||||
|
|
@ -153,18 +265,6 @@ config OC_ETM
|
|||
buffer driver that will allow you to collect traces of the
|
||||
kernel code.
|
||||
|
||||
config DEBUG_S3C_UART
|
||||
depends on PLAT_SAMSUNG
|
||||
int "S3C UART to use for low-level debug"
|
||||
default "0"
|
||||
help
|
||||
Choice for UART for kernel low-level using S3C UARTS,
|
||||
should be between zero and two. The port must have been
|
||||
initialised by the boot-loader before use.
|
||||
|
||||
The uncompressor code port configuration is now handled
|
||||
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
||||
|
||||
config ARM_KPROBES_TEST
|
||||
tristate "Kprobes test module"
|
||||
depends on KPROBES && MODULES
|
||||
|
|
|
|||
|
|
@ -159,7 +159,7 @@ machine-$(CONFIG_ARCH_MMP) := mmp
|
|||
machine-$(CONFIG_ARCH_MSM) := msm
|
||||
machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0
|
||||
machine-$(CONFIG_ARCH_IMX_V4_V5) := imx
|
||||
machine-$(CONFIG_ARCH_MX3) := imx
|
||||
machine-$(CONFIG_ARCH_IMX_V6_V7) := imx
|
||||
machine-$(CONFIG_ARCH_MX5) := mx5
|
||||
machine-$(CONFIG_ARCH_MXS) := mxs
|
||||
machine-$(CONFIG_ARCH_NETX) := netx
|
||||
|
|
|
|||
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "imx6q.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX6 Quad SABRE Automotive Board";
|
||||
compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttymxc0,115200 root=/dev/mmcblk3p3 rootwait";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x80000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
aips-bus@02100000 { /* AIPS2 */
|
||||
enet@02188000 {
|
||||
phy-mode = "rgmii";
|
||||
local-mac-address = [00 04 9F 01 1B 61];
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usdhc@02198000 { /* uSDHC3 */
|
||||
cd-gpios = <&gpio5 11 0>; /* GPIO6_11 */
|
||||
wp-gpios = <&gpio5 14 0>; /* GPIO6_14 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usdhc@0219c000 { /* uSDHC4 */
|
||||
fsl,card-wired;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart3: uart@021f0000 { /* UART4 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
debug-led {
|
||||
label = "Heartbeat";
|
||||
gpios = <&gpio2 25 0>; /* GPIO3_25 */
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,575 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
serial4 = &uart4;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <2>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <3>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
intc: interrupt-controller@00a01000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0x00a01000 0x1000>,
|
||||
<0x00a00100 0x100>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ckil {
|
||||
compatible = "fsl,imx-ckil", "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
ckih1 {
|
||||
compatible = "fsl,imx-ckih1", "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
osc {
|
||||
compatible = "fsl,imx-osc", "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&intc>;
|
||||
ranges;
|
||||
|
||||
timer@00a00600 {
|
||||
compatible = "arm,smp-twd";
|
||||
reg = <0x00a00600 0x100>;
|
||||
interrupts = <1 13 0xf4>;
|
||||
};
|
||||
|
||||
L2: l2-cache@00a02000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x00a02000 0x1000>;
|
||||
interrupts = <0 92 0x04>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
aips-bus@02000000 { /* AIPS1 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x02000000 0x100000>;
|
||||
ranges;
|
||||
|
||||
spba-bus@02000000 {
|
||||
compatible = "fsl,spba-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x02000000 0x40000>;
|
||||
ranges;
|
||||
|
||||
spdif@02004000 {
|
||||
reg = <0x02004000 0x4000>;
|
||||
interrupts = <0 52 0x04>;
|
||||
};
|
||||
|
||||
ecspi@02008000 { /* eCSPI1 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02008000 0x4000>;
|
||||
interrupts = <0 31 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi@0200c000 { /* eCSPI2 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x0200c000 0x4000>;
|
||||
interrupts = <0 32 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi@02010000 { /* eCSPI3 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02010000 0x4000>;
|
||||
interrupts = <0 33 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi@02014000 { /* eCSPI4 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02014000 0x4000>;
|
||||
interrupts = <0 34 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi@02018000 { /* eCSPI5 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02018000 0x4000>;
|
||||
interrupts = <0 35 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: uart@02020000 { /* UART1 */
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02020000 0x4000>;
|
||||
interrupts = <0 26 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esai@02024000 {
|
||||
reg = <0x02024000 0x4000>;
|
||||
interrupts = <0 51 0x04>;
|
||||
};
|
||||
|
||||
ssi@02028000 { /* SSI1 */
|
||||
reg = <0x02028000 0x4000>;
|
||||
interrupts = <0 46 0x04>;
|
||||
};
|
||||
|
||||
ssi@0202c000 { /* SSI2 */
|
||||
reg = <0x0202c000 0x4000>;
|
||||
interrupts = <0 47 0x04>;
|
||||
};
|
||||
|
||||
ssi@02030000 { /* SSI3 */
|
||||
reg = <0x02030000 0x4000>;
|
||||
interrupts = <0 48 0x04>;
|
||||
};
|
||||
|
||||
asrc@02034000 {
|
||||
reg = <0x02034000 0x4000>;
|
||||
interrupts = <0 50 0x04>;
|
||||
};
|
||||
|
||||
spba@0203c000 {
|
||||
reg = <0x0203c000 0x4000>;
|
||||
};
|
||||
};
|
||||
|
||||
vpu@02040000 {
|
||||
reg = <0x02040000 0x3c000>;
|
||||
interrupts = <0 3 0x04 0 12 0x04>;
|
||||
};
|
||||
|
||||
aipstz@0207c000 { /* AIPSTZ1 */
|
||||
reg = <0x0207c000 0x4000>;
|
||||
};
|
||||
|
||||
pwm@02080000 { /* PWM1 */
|
||||
reg = <0x02080000 0x4000>;
|
||||
interrupts = <0 83 0x04>;
|
||||
};
|
||||
|
||||
pwm@02084000 { /* PWM2 */
|
||||
reg = <0x02084000 0x4000>;
|
||||
interrupts = <0 84 0x04>;
|
||||
};
|
||||
|
||||
pwm@02088000 { /* PWM3 */
|
||||
reg = <0x02088000 0x4000>;
|
||||
interrupts = <0 85 0x04>;
|
||||
};
|
||||
|
||||
pwm@0208c000 { /* PWM4 */
|
||||
reg = <0x0208c000 0x4000>;
|
||||
interrupts = <0 86 0x04>;
|
||||
};
|
||||
|
||||
flexcan@02090000 { /* CAN1 */
|
||||
reg = <0x02090000 0x4000>;
|
||||
interrupts = <0 110 0x04>;
|
||||
};
|
||||
|
||||
flexcan@02094000 { /* CAN2 */
|
||||
reg = <0x02094000 0x4000>;
|
||||
interrupts = <0 111 0x04>;
|
||||
};
|
||||
|
||||
gpt@02098000 {
|
||||
compatible = "fsl,imx6q-gpt";
|
||||
reg = <0x02098000 0x4000>;
|
||||
interrupts = <0 55 0x04>;
|
||||
};
|
||||
|
||||
gpio0: gpio@0209c000 { /* GPIO1 */
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x0209c000 0x4000>;
|
||||
interrupts = <0 66 0x04 0 67 0x04>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio1: gpio@020a0000 { /* GPIO2 */
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x020a0000 0x4000>;
|
||||
interrupts = <0 68 0x04 0 69 0x04>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio2: gpio@020a4000 { /* GPIO3 */
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x020a4000 0x4000>;
|
||||
interrupts = <0 70 0x04 0 71 0x04>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio3: gpio@020a8000 { /* GPIO4 */
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x020a8000 0x4000>;
|
||||
interrupts = <0 72 0x04 0 73 0x04>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio4: gpio@020ac000 { /* GPIO5 */
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x020ac000 0x4000>;
|
||||
interrupts = <0 74 0x04 0 75 0x04>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio5: gpio@020b0000 { /* GPIO6 */
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x020b0000 0x4000>;
|
||||
interrupts = <0 76 0x04 0 77 0x04>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gpio6: gpio@020b4000 { /* GPIO7 */
|
||||
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
|
||||
reg = <0x020b4000 0x4000>;
|
||||
interrupts = <0 78 0x04 0 79 0x04>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
kpp@020b8000 {
|
||||
reg = <0x020b8000 0x4000>;
|
||||
interrupts = <0 82 0x04>;
|
||||
};
|
||||
|
||||
wdog@020bc000 { /* WDOG1 */
|
||||
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x020bc000 0x4000>;
|
||||
interrupts = <0 80 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog@020c0000 { /* WDOG2 */
|
||||
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x020c0000 0x4000>;
|
||||
interrupts = <0 81 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ccm@020c4000 {
|
||||
compatible = "fsl,imx6q-ccm";
|
||||
reg = <0x020c4000 0x4000>;
|
||||
interrupts = <0 87 0x04 0 88 0x04>;
|
||||
};
|
||||
|
||||
anatop@020c8000 {
|
||||
compatible = "fsl,imx6q-anatop";
|
||||
reg = <0x020c8000 0x1000>;
|
||||
interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
|
||||
};
|
||||
|
||||
usbphy@020c9000 { /* USBPHY1 */
|
||||
reg = <0x020c9000 0x1000>;
|
||||
interrupts = <0 44 0x04>;
|
||||
};
|
||||
|
||||
usbphy@020ca000 { /* USBPHY2 */
|
||||
reg = <0x020ca000 0x1000>;
|
||||
interrupts = <0 45 0x04>;
|
||||
};
|
||||
|
||||
snvs@020cc000 {
|
||||
reg = <0x020cc000 0x4000>;
|
||||
interrupts = <0 19 0x04 0 20 0x04>;
|
||||
};
|
||||
|
||||
epit@020d0000 { /* EPIT1 */
|
||||
reg = <0x020d0000 0x4000>;
|
||||
interrupts = <0 56 0x04>;
|
||||
};
|
||||
|
||||
epit@020d4000 { /* EPIT2 */
|
||||
reg = <0x020d4000 0x4000>;
|
||||
interrupts = <0 57 0x04>;
|
||||
};
|
||||
|
||||
src@020d8000 {
|
||||
compatible = "fsl,imx6q-src";
|
||||
reg = <0x020d8000 0x4000>;
|
||||
interrupts = <0 91 0x04 0 96 0x04>;
|
||||
};
|
||||
|
||||
gpc@020dc000 {
|
||||
compatible = "fsl,imx6q-gpc";
|
||||
reg = <0x020dc000 0x4000>;
|
||||
interrupts = <0 89 0x04 0 90 0x04>;
|
||||
};
|
||||
|
||||
iomuxc@020e0000 {
|
||||
reg = <0x020e0000 0x4000>;
|
||||
};
|
||||
|
||||
dcic@020e4000 { /* DCIC1 */
|
||||
reg = <0x020e4000 0x4000>;
|
||||
interrupts = <0 124 0x04>;
|
||||
};
|
||||
|
||||
dcic@020e8000 { /* DCIC2 */
|
||||
reg = <0x020e8000 0x4000>;
|
||||
interrupts = <0 125 0x04>;
|
||||
};
|
||||
|
||||
sdma@020ec000 {
|
||||
compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
|
||||
reg = <0x020ec000 0x4000>;
|
||||
interrupts = <0 2 0x04>;
|
||||
};
|
||||
};
|
||||
|
||||
aips-bus@02100000 { /* AIPS2 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x02100000 0x100000>;
|
||||
ranges;
|
||||
|
||||
caam@02100000 {
|
||||
reg = <0x02100000 0x40000>;
|
||||
interrupts = <0 105 0x04 0 106 0x04>;
|
||||
};
|
||||
|
||||
aipstz@0217c000 { /* AIPSTZ2 */
|
||||
reg = <0x0217c000 0x4000>;
|
||||
};
|
||||
|
||||
enet@02188000 {
|
||||
compatible = "fsl,imx6q-fec";
|
||||
reg = <0x02188000 0x4000>;
|
||||
interrupts = <0 118 0x04 0 119 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mlb@0218c000 {
|
||||
reg = <0x0218c000 0x4000>;
|
||||
interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
|
||||
};
|
||||
|
||||
usdhc@02190000 { /* uSDHC1 */
|
||||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x02190000 0x4000>;
|
||||
interrupts = <0 22 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc@02194000 { /* uSDHC2 */
|
||||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x02194000 0x4000>;
|
||||
interrupts = <0 23 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc@02198000 { /* uSDHC3 */
|
||||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x02198000 0x4000>;
|
||||
interrupts = <0 24 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc@0219c000 { /* uSDHC4 */
|
||||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x0219c000 0x4000>;
|
||||
interrupts = <0 25 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@021a0000 { /* I2C1 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
|
||||
reg = <0x021a0000 0x4000>;
|
||||
interrupts = <0 36 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@021a4000 { /* I2C2 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
|
||||
reg = <0x021a4000 0x4000>;
|
||||
interrupts = <0 37 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@021a8000 { /* I2C3 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
|
||||
reg = <0x021a8000 0x4000>;
|
||||
interrupts = <0 38 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
romcp@021ac000 {
|
||||
reg = <0x021ac000 0x4000>;
|
||||
};
|
||||
|
||||
mmdc@021b0000 { /* MMDC0 */
|
||||
compatible = "fsl,imx6q-mmdc";
|
||||
reg = <0x021b0000 0x4000>;
|
||||
};
|
||||
|
||||
mmdc@021b4000 { /* MMDC1 */
|
||||
reg = <0x021b4000 0x4000>;
|
||||
};
|
||||
|
||||
weim@021b8000 {
|
||||
reg = <0x021b8000 0x4000>;
|
||||
interrupts = <0 14 0x04>;
|
||||
};
|
||||
|
||||
ocotp@021bc000 {
|
||||
reg = <0x021bc000 0x4000>;
|
||||
};
|
||||
|
||||
ocotp@021c0000 {
|
||||
reg = <0x021c0000 0x4000>;
|
||||
interrupts = <0 21 0x04>;
|
||||
};
|
||||
|
||||
tzasc@021d0000 { /* TZASC1 */
|
||||
reg = <0x021d0000 0x4000>;
|
||||
interrupts = <0 108 0x04>;
|
||||
};
|
||||
|
||||
tzasc@021d4000 { /* TZASC2 */
|
||||
reg = <0x021d4000 0x4000>;
|
||||
interrupts = <0 109 0x04>;
|
||||
};
|
||||
|
||||
audmux@021d8000 {
|
||||
reg = <0x021d8000 0x4000>;
|
||||
};
|
||||
|
||||
mipi@021dc000 { /* MIPI-CSI */
|
||||
reg = <0x021dc000 0x4000>;
|
||||
};
|
||||
|
||||
mipi@021e0000 { /* MIPI-DSI */
|
||||
reg = <0x021e0000 0x4000>;
|
||||
};
|
||||
|
||||
vdoa@021e4000 {
|
||||
reg = <0x021e4000 0x4000>;
|
||||
interrupts = <0 18 0x04>;
|
||||
};
|
||||
|
||||
uart1: uart@021e8000 { /* UART2 */
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021e8000 0x4000>;
|
||||
interrupts = <0 27 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: uart@021ec000 { /* UART3 */
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021ec000 0x4000>;
|
||||
interrupts = <0 28 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: uart@021f0000 { /* UART4 */
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021f0000 0x4000>;
|
||||
interrupts = <0 29 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: uart@021f4000 { /* UART5 */
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021f4000 0x4000>;
|
||||
interrupts = <0 30 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,5 +1,15 @@
|
|||
config IMX_HAVE_DMA_V1
|
||||
bool
|
||||
|
||||
config HAVE_IMX_GPC
|
||||
bool
|
||||
|
||||
config HAVE_IMX_MMDC
|
||||
bool
|
||||
|
||||
config HAVE_IMX_SRC
|
||||
bool
|
||||
|
||||
#
|
||||
# ARCH_MX31 and ARCH_MX35 are left for compatibility
|
||||
# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.
|
||||
|
|
@ -64,6 +74,7 @@ config SOC_IMX31
|
|||
select ARCH_MXC_AUDMUX_V2
|
||||
select ARCH_MX31
|
||||
select MXC_AVIC
|
||||
select SMP_ON_UP if SMP
|
||||
|
||||
config SOC_IMX35
|
||||
bool
|
||||
|
|
@ -73,6 +84,7 @@ config SOC_IMX35
|
|||
select HAVE_EPIT
|
||||
select ARCH_MX35
|
||||
select MXC_AVIC
|
||||
select SMP_ON_UP if SMP
|
||||
|
||||
|
||||
if ARCH_IMX_V4_V5
|
||||
|
|
@ -341,7 +353,7 @@ config MACH_IMX27IPCAM
|
|||
|
||||
endif
|
||||
|
||||
if ARCH_MX3
|
||||
if ARCH_IMX_V6_V7
|
||||
|
||||
comment "MX31 platforms:"
|
||||
|
||||
|
|
@ -591,4 +603,20 @@ config MACH_VPR200
|
|||
Include support for VPR200 platform. This includes specific
|
||||
configurations for the board and its peripherals.
|
||||
|
||||
comment "i.MX6 family:"
|
||||
|
||||
config SOC_IMX6Q
|
||||
bool "i.MX6 Quad support"
|
||||
select ARM_GIC
|
||||
select CACHE_L2X0
|
||||
select CPU_V7
|
||||
select HAVE_ARM_SCU
|
||||
select HAVE_IMX_GPC
|
||||
select HAVE_IMX_MMDC
|
||||
select HAVE_IMX_SRC
|
||||
select USE_OF
|
||||
|
||||
help
|
||||
This enables support for Freescale i.MX6 Quad processor.
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -60,3 +60,14 @@ obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
|
|||
obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o
|
||||
obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
|
||||
obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
|
||||
|
||||
obj-$(CONFIG_DEBUG_LL) += lluart.o
|
||||
obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
|
||||
obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
|
||||
obj-$(CONFIG_HAVE_IMX_SRC) += src.o
|
||||
obj-$(CONFIG_CPU_V7) += head-v7.o
|
||||
AFLAGS_head-v7.o :=-Wa,-march=armv7-a
|
||||
obj-$(CONFIG_SMP) += platsmp.o
|
||||
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
|
||||
obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o
|
||||
|
|
|
|||
|
|
@ -17,3 +17,7 @@ initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000
|
|||
zreladdr-$(CONFIG_ARCH_MX3) := 0x80008000
|
||||
params_phys-$(CONFIG_ARCH_MX3) := 0x80000100
|
||||
initrd_phys-$(CONFIG_ARCH_MX3) := 0x80800000
|
||||
|
||||
zreladdr-$(CONFIG_SOC_IMX6Q) += 0x10008000
|
||||
params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100
|
||||
initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
|
||||
#define GPC_IMR1 0x008
|
||||
#define GPC_PGC_CPU_PDN 0x2a0
|
||||
|
||||
#define IMR_NUM 4
|
||||
|
||||
static void __iomem *gpc_base;
|
||||
static u32 gpc_wake_irqs[IMR_NUM];
|
||||
static u32 gpc_saved_imrs[IMR_NUM];
|
||||
|
||||
void imx_gpc_pre_suspend(void)
|
||||
{
|
||||
void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
|
||||
int i;
|
||||
|
||||
/* Tell GPC to power off ARM core when suspend */
|
||||
writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
|
||||
|
||||
for (i = 0; i < IMR_NUM; i++) {
|
||||
gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
|
||||
writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
|
||||
}
|
||||
}
|
||||
|
||||
void imx_gpc_post_resume(void)
|
||||
{
|
||||
void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
|
||||
int i;
|
||||
|
||||
/* Keep ARM core powered on for other low-power modes */
|
||||
writel_relaxed(0x0, gpc_base + GPC_PGC_CPU_PDN);
|
||||
|
||||
for (i = 0; i < IMR_NUM; i++)
|
||||
writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
|
||||
}
|
||||
|
||||
static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
|
||||
{
|
||||
unsigned int idx = d->irq / 32 - 1;
|
||||
u32 mask;
|
||||
|
||||
/* Sanity check for SPI irq */
|
||||
if (d->irq < 32)
|
||||
return -EINVAL;
|
||||
|
||||
mask = 1 << d->irq % 32;
|
||||
gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
|
||||
gpc_wake_irqs[idx] & ~mask;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void imx_gpc_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
void __iomem *reg;
|
||||
u32 val;
|
||||
|
||||
/* Sanity check for SPI irq */
|
||||
if (d->irq < 32)
|
||||
return;
|
||||
|
||||
reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
|
||||
val = readl_relaxed(reg);
|
||||
val &= ~(1 << d->irq % 32);
|
||||
writel_relaxed(val, reg);
|
||||
}
|
||||
|
||||
static void imx_gpc_irq_mask(struct irq_data *d)
|
||||
{
|
||||
void __iomem *reg;
|
||||
u32 val;
|
||||
|
||||
/* Sanity check for SPI irq */
|
||||
if (d->irq < 32)
|
||||
return;
|
||||
|
||||
reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
|
||||
val = readl_relaxed(reg);
|
||||
val |= 1 << (d->irq % 32);
|
||||
writel_relaxed(val, reg);
|
||||
}
|
||||
|
||||
void __init imx_gpc_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
|
||||
gpc_base = of_iomap(np, 0);
|
||||
WARN_ON(!gpc_base);
|
||||
|
||||
/* Register GPC as the secondary interrupt controller behind GIC */
|
||||
gic_arch_extn.irq_mask = imx_gpc_irq_mask;
|
||||
gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
|
||||
gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;
|
||||
}
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/init.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
|
||||
.section ".text.head", "ax"
|
||||
__CPUINIT
|
||||
|
||||
/*
|
||||
* The secondary kernel init calls v7_flush_dcache_all before it enables
|
||||
* the L1; however, the L1 comes out of reset in an undefined state, so
|
||||
* the clean + invalidate performed by v7_flush_dcache_all causes a bunch
|
||||
* of cache lines with uninitialized data and uninitialized tags to get
|
||||
* written out to memory, which does really unpleasant things to the main
|
||||
* processor. We fix this by performing an invalidate, rather than a
|
||||
* clean + invalidate, before jumping into the kernel.
|
||||
*
|
||||
* This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
|
||||
* to be called for both secondary cores startup and primary core resume
|
||||
* procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S.
|
||||
*/
|
||||
ENTRY(v7_invalidate_l1)
|
||||
mov r0, #0
|
||||
mcr p15, 2, r0, c0, c0, 0
|
||||
mrc p15, 1, r0, c0, c0, 0
|
||||
|
||||
ldr r1, =0x7fff
|
||||
and r2, r1, r0, lsr #13
|
||||
|
||||
ldr r1, =0x3ff
|
||||
|
||||
and r3, r1, r0, lsr #3 @ NumWays - 1
|
||||
add r2, r2, #1 @ NumSets
|
||||
|
||||
and r0, r0, #0x7
|
||||
add r0, r0, #4 @ SetShift
|
||||
|
||||
clz r1, r3 @ WayShift
|
||||
add r4, r3, #1 @ NumWays
|
||||
1: sub r2, r2, #1 @ NumSets--
|
||||
mov r3, r4 @ Temp = NumWays
|
||||
2: subs r3, r3, #1 @ Temp--
|
||||
mov r5, r3, lsl r1
|
||||
mov r6, r2, lsl r0
|
||||
orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
|
||||
mcr p15, 0, r5, c7, c6, 2
|
||||
bgt 2b
|
||||
cmp r2, #0
|
||||
bgt 1b
|
||||
dsb
|
||||
isb
|
||||
mov pc, lr
|
||||
ENDPROC(v7_invalidate_l1)
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
ENTRY(v7_secondary_startup)
|
||||
bl v7_invalidate_l1
|
||||
b secondary_startup
|
||||
ENDPROC(v7_secondary_startup)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The following code is located into the .data section. This is to
|
||||
* allow phys_l2x0_saved_regs to be accessed with a relative load
|
||||
* as we are running on physical address here.
|
||||
*/
|
||||
.data
|
||||
.align
|
||||
|
||||
.macro pl310_resume
|
||||
ldr r2, phys_l2x0_saved_regs
|
||||
ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0
|
||||
ldr r1, [r2, #L2X0_R_AUX_CTRL] @ get aux_ctrl value
|
||||
str r1, [r0, #L2X0_AUX_CTRL] @ restore aux_ctrl
|
||||
mov r1, #0x1
|
||||
str r1, [r0, #L2X0_CTRL] @ re-enable L2
|
||||
.endm
|
||||
|
||||
ENTRY(v7_cpu_resume)
|
||||
bl v7_invalidate_l1
|
||||
pl310_resume
|
||||
b cpu_resume
|
||||
ENDPROC(v7_cpu_resume)
|
||||
|
||||
.globl phys_l2x0_saved_regs
|
||||
phys_l2x0_saved_regs:
|
||||
.long 0
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/errno.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <mach/common.h>
|
||||
|
||||
int platform_cpu_kill(unsigned int cpu)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* platform-specific code to shutdown a CPU
|
||||
*
|
||||
* Called with IRQs disabled
|
||||
*/
|
||||
void platform_cpu_die(unsigned int cpu)
|
||||
{
|
||||
flush_cache_all();
|
||||
imx_enable_cpu(cpu, false);
|
||||
cpu_do_idle();
|
||||
|
||||
/* We should never return from idle */
|
||||
panic("cpu %d unexpectedly exit from shutdown\n", cpu);
|
||||
}
|
||||
|
||||
int platform_cpu_disable(unsigned int cpu)
|
||||
{
|
||||
/*
|
||||
* we don't allow CPU 0 to be shutdown (it is still too special
|
||||
* e.g. clock tick interrupts)
|
||||
*/
|
||||
return cpu == 0 ? -EPERM : 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/sizes.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <mach/hardware.h>
|
||||
|
||||
static struct map_desc imx_lluart_desc = {
|
||||
#ifdef CONFIG_DEBUG_IMX6Q_UART
|
||||
.virtual = MX6Q_IO_P2V(MX6Q_UART4_BASE_ADDR),
|
||||
.pfn = __phys_to_pfn(MX6Q_UART4_BASE_ADDR),
|
||||
.length = MX6Q_UART4_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
#endif
|
||||
};
|
||||
|
||||
void __init imx_lluart_map_io(void)
|
||||
{
|
||||
if (imx_lluart_desc.virtual)
|
||||
iotable_init(&imx_lluart_desc, 1);
|
||||
}
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/clockchips.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <asm/smp_twd.h>
|
||||
|
||||
/*
|
||||
* Setup the local clock events for a CPU.
|
||||
*/
|
||||
int __cpuinit local_timer_setup(struct clock_event_device *evt)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "arm,smp-twd");
|
||||
if (!twd_base) {
|
||||
twd_base = of_iomap(np, 0);
|
||||
WARN_ON(!twd_base);
|
||||
}
|
||||
evt->irq = irq_of_parse_and_map(np, 0);
|
||||
twd_timer_setup(evt);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/hardware.h>
|
||||
|
||||
static void __init imx6q_init_machine(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
|
||||
imx6q_pm_init();
|
||||
}
|
||||
|
||||
static void __init imx6q_map_io(void)
|
||||
{
|
||||
imx_lluart_map_io();
|
||||
imx_scu_map_io();
|
||||
}
|
||||
|
||||
static void __init imx6q_gpio_add_irq_domain(struct device_node *np,
|
||||
struct device_node *interrupt_parent)
|
||||
{
|
||||
static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS -
|
||||
32 * 7; /* imx6q gets 7 gpio ports */
|
||||
|
||||
irq_domain_add_simple(np, gpio_irq_base);
|
||||
gpio_irq_base += 32;
|
||||
}
|
||||
|
||||
static const struct of_device_id imx6q_irq_match[] __initconst = {
|
||||
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
|
||||
{ .compatible = "fsl,imx6q-gpio", .data = imx6q_gpio_add_irq_domain, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static void __init imx6q_init_irq(void)
|
||||
{
|
||||
l2x0_of_init(0, ~0UL);
|
||||
imx_src_init();
|
||||
imx_gpc_init();
|
||||
of_irq_init(imx6q_irq_match);
|
||||
}
|
||||
|
||||
static void __init imx6q_timer_init(void)
|
||||
{
|
||||
mx6q_clocks_init();
|
||||
}
|
||||
|
||||
static struct sys_timer imx6q_timer = {
|
||||
.init = imx6q_timer_init,
|
||||
};
|
||||
|
||||
static const char *imx6q_dt_compat[] __initdata = {
|
||||
"fsl,imx6q-sabreauto",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)")
|
||||
.map_io = imx6q_map_io,
|
||||
.init_irq = imx6q_init_irq,
|
||||
.handle_irq = imx6q_handle_irq,
|
||||
.timer = &imx6q_timer,
|
||||
.init_machine = imx6q_init_machine,
|
||||
.dt_compat = imx6q_dt_compat,
|
||||
MACHINE_END
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
|
||||
#define MMDC_MAPSR 0x404
|
||||
#define BP_MMDC_MAPSR_PSD 0
|
||||
#define BP_MMDC_MAPSR_PSS 4
|
||||
|
||||
static int __devinit imx_mmdc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
void __iomem *mmdc_base, *reg;
|
||||
u32 val;
|
||||
int timeout = 0x400;
|
||||
|
||||
mmdc_base = of_iomap(np, 0);
|
||||
WARN_ON(!mmdc_base);
|
||||
|
||||
reg = mmdc_base + MMDC_MAPSR;
|
||||
|
||||
/* Enable automatic power saving */
|
||||
val = readl_relaxed(reg);
|
||||
val &= ~(1 << BP_MMDC_MAPSR_PSD);
|
||||
writel_relaxed(val, reg);
|
||||
|
||||
/* Ensure it's successfully enabled */
|
||||
while (!(readl_relaxed(reg) & 1 << BP_MMDC_MAPSR_PSS) && --timeout)
|
||||
cpu_relax();
|
||||
|
||||
if (unlikely(!timeout)) {
|
||||
pr_warn("%s: failed to enable automatic power saving\n",
|
||||
__func__);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct of_device_id imx_mmdc_dt_ids[] = {
|
||||
{ .compatible = "fsl,imx6q-mmdc", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static struct platform_driver imx_mmdc_driver = {
|
||||
.driver = {
|
||||
.name = "imx-mmdc",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = imx_mmdc_dt_ids,
|
||||
},
|
||||
.probe = imx_mmdc_probe,
|
||||
};
|
||||
|
||||
static int __init imx_mmdc_init(void)
|
||||
{
|
||||
return platform_driver_register(&imx_mmdc_driver);
|
||||
}
|
||||
postcore_initcall(imx_mmdc_init);
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/smp.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/smp_scu.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/hardware.h>
|
||||
|
||||
static void __iomem *scu_base;
|
||||
|
||||
static struct map_desc scu_io_desc __initdata = {
|
||||
/* .virtual and .pfn are run-time assigned */
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
};
|
||||
|
||||
void __init imx_scu_map_io(void)
|
||||
{
|
||||
unsigned long base;
|
||||
|
||||
/* Get SCU base */
|
||||
asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
|
||||
|
||||
scu_io_desc.virtual = IMX_IO_P2V(base);
|
||||
scu_io_desc.pfn = __phys_to_pfn(base);
|
||||
iotable_init(&scu_io_desc, 1);
|
||||
|
||||
scu_base = IMX_IO_ADDRESS(base);
|
||||
}
|
||||
|
||||
void __cpuinit platform_secondary_init(unsigned int cpu)
|
||||
{
|
||||
/*
|
||||
* if any interrupts are already enabled for the primary
|
||||
* core (e.g. timer irq), then they will not have been enabled
|
||||
* for us: do so
|
||||
*/
|
||||
gic_secondary_init(0);
|
||||
}
|
||||
|
||||
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
imx_set_cpu_jump(cpu, v7_secondary_startup);
|
||||
imx_enable_cpu(cpu, true);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialise the CPU possible map early - this describes the CPUs
|
||||
* which may be present or become present in the system.
|
||||
*/
|
||||
void __init smp_init_cpus(void)
|
||||
{
|
||||
int i, ncores;
|
||||
|
||||
ncores = scu_get_core_count(scu_base);
|
||||
|
||||
for (i = 0; i < ncores; i++)
|
||||
set_cpu_possible(i, true);
|
||||
|
||||
set_smp_cross_call(gic_raise_softirq);
|
||||
}
|
||||
|
||||
void imx_smp_prepare(void)
|
||||
{
|
||||
scu_enable(scu_base);
|
||||
}
|
||||
|
||||
void __init platform_smp_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
imx_smp_prepare();
|
||||
}
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/suspend.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/proc-fns.h>
|
||||
#include <asm/suspend.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/hardware.h>
|
||||
|
||||
extern unsigned long phys_l2x0_saved_regs;
|
||||
|
||||
static int imx6q_suspend_finish(unsigned long val)
|
||||
{
|
||||
cpu_do_idle();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int imx6q_pm_enter(suspend_state_t state)
|
||||
{
|
||||
switch (state) {
|
||||
case PM_SUSPEND_MEM:
|
||||
imx6q_set_lpm(STOP_POWER_OFF);
|
||||
imx_gpc_pre_suspend();
|
||||
imx_set_cpu_jump(0, v7_cpu_resume);
|
||||
/* Zzz ... */
|
||||
cpu_suspend(0, imx6q_suspend_finish);
|
||||
imx_smp_prepare();
|
||||
imx_gpc_post_resume();
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct platform_suspend_ops imx6q_pm_ops = {
|
||||
.enter = imx6q_pm_enter,
|
||||
.valid = suspend_valid_only_mem,
|
||||
};
|
||||
|
||||
void __init imx6q_pm_init(void)
|
||||
{
|
||||
/*
|
||||
* The l2x0 core code provides an infrastucture to save and restore
|
||||
* l2x0 registers across suspend/resume cycle. But because imx6q
|
||||
* retains L2 content during suspend and needs to resume L2 before
|
||||
* MMU is enabled, it can only utilize register saving support and
|
||||
* have to take care of restoring on its own. So we save physical
|
||||
* address of the data structure used by l2x0 core to save registers,
|
||||
* and later restore the necessary ones in imx6q resume entry.
|
||||
*/
|
||||
phys_l2x0_saved_regs = __pa(&l2x0_saved_regs);
|
||||
|
||||
suspend_set_ops(&imx6q_pm_ops);
|
||||
}
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <asm/unified.h>
|
||||
|
||||
#define SRC_SCR 0x000
|
||||
#define SRC_GPR1 0x020
|
||||
#define BP_SRC_SCR_CORE1_RST 14
|
||||
#define BP_SRC_SCR_CORE1_ENABLE 22
|
||||
|
||||
static void __iomem *src_base;
|
||||
|
||||
void imx_enable_cpu(int cpu, bool enable)
|
||||
{
|
||||
u32 mask, val;
|
||||
|
||||
mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
|
||||
val = readl_relaxed(src_base + SRC_SCR);
|
||||
val = enable ? val | mask : val & ~mask;
|
||||
writel_relaxed(val, src_base + SRC_SCR);
|
||||
}
|
||||
|
||||
void imx_set_cpu_jump(int cpu, void *jump_addr)
|
||||
{
|
||||
writel_relaxed(BSYM(virt_to_phys(jump_addr)),
|
||||
src_base + SRC_GPR1 + cpu * 8);
|
||||
}
|
||||
|
||||
void __init imx_src_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src");
|
||||
src_base = of_iomap(np, 0);
|
||||
WARN_ON(!src_base);
|
||||
}
|
||||
|
|
@ -14,17 +14,9 @@
|
|||
#include <mach/mx23.h>
|
||||
#include <mach/mx28.h>
|
||||
|
||||
#ifdef CONFIG_SOC_IMX23
|
||||
#ifdef UART_PADDR
|
||||
#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
|
||||
#endif
|
||||
#ifdef CONFIG_DEBUG_IMX23_UART
|
||||
#define UART_PADDR MX23_DUART_BASE_ADDR
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_IMX28
|
||||
#ifdef UART_PADDR
|
||||
#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
|
||||
#endif
|
||||
#elif defined (CONFIG_DEBUG_IMX28_UART)
|
||||
#define UART_PADDR MX28_DUART_BASE_ADDR
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -10,23 +10,10 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_MACH_REALVIEW_EB) || \
|
||||
defined(CONFIG_MACH_REALVIEW_PB11MP) || \
|
||||
defined(CONFIG_MACH_REALVIEW_PBA8) || \
|
||||
defined(CONFIG_MACH_REALVIEW_PBX)
|
||||
#ifndef DEBUG_LL_UART_OFFSET
|
||||
#ifdef CONFIG_DEBUG_REALVIEW_STD_PORT
|
||||
#define DEBUG_LL_UART_OFFSET 0x00009000
|
||||
#elif DEBUG_LL_UART_OFFSET != 0x00009000
|
||||
#warning "DEBUG_LL_UART_OFFSET already defined to a different value"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_REALVIEW_PB1176
|
||||
#ifndef DEBUG_LL_UART_OFFSET
|
||||
#elif defined(CONFIG_DEBUG_REALVIEW_PB1176_PORT)
|
||||
#define DEBUG_LL_UART_OFFSET 0x0010c000
|
||||
#elif DEBUG_LL_UART_OFFSET != 0x0010c000
|
||||
#warning "DEBUG_LL_UART_OFFSET already defined to a different value"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef DEBUG_LL_UART_OFFSET
|
||||
|
|
|
|||
|
|
@ -819,7 +819,7 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
|
|||
config CACHE_L2X0
|
||||
bool "Enable the L2x0 outer cache controller"
|
||||
depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
|
||||
REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
|
||||
REALVIEW_EB_A9MP || ARCH_IMX_V6_V7 || MACH_REALVIEW_PBX || \
|
||||
ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
|
||||
ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \
|
||||
ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX || ARCH_HIGHBANK
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ menu "Freescale MXC Implementations"
|
|||
|
||||
choice
|
||||
prompt "Freescale CPU family:"
|
||||
default ARCH_MX3
|
||||
default ARCH_IMX_V6_V7
|
||||
|
||||
config ARCH_IMX_V4_V5
|
||||
bool "i.MX1, i.MX21, i.MX25, i.MX27"
|
||||
|
|
@ -16,10 +16,13 @@ config ARCH_IMX_V4_V5
|
|||
This enables support for systems based on the Freescale i.MX ARMv4
|
||||
and ARMv5 SoCs
|
||||
|
||||
config ARCH_MX3
|
||||
bool "MX3-based"
|
||||
config ARCH_IMX_V6_V7
|
||||
bool "i.MX3, i.MX6"
|
||||
select AUTO_ZRELADDR if !ZBOOT_ROM
|
||||
select ARM_PATCH_PHYS_VIRT
|
||||
help
|
||||
This enables support for systems based on the Freescale i.MX3 family
|
||||
This enables support for systems based on the Freescale i.MX3 and i.MX6
|
||||
family.
|
||||
|
||||
config ARCH_MX5
|
||||
bool "i.MX50, i.MX51, i.MX53"
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
# Common support
|
||||
obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o
|
||||
|
||||
# MX51 uses the TZIC interrupt controller, older platforms use AVIC
|
||||
obj-$(CONFIG_ARM_GIC) += gic.o
|
||||
obj-$(CONFIG_MXC_TZIC) += tzic.o
|
||||
obj-$(CONFIG_MXC_AVIC) += avic.o
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <asm/exception.h>
|
||||
#include <asm/localtimer.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#ifdef CONFIG_SMP
|
||||
#include <asm/smp.h>
|
||||
#endif
|
||||
|
||||
asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
|
||||
{
|
||||
u32 irqstat, irqnr;
|
||||
|
||||
do {
|
||||
irqstat = readl_relaxed(gic_cpu_base_addr + GIC_CPU_INTACK);
|
||||
irqnr = irqstat & 0x3ff;
|
||||
if (irqnr == 1023)
|
||||
break;
|
||||
|
||||
if (irqnr > 29 && irqnr < 1021)
|
||||
handle_IRQ(irqnr, regs);
|
||||
#ifdef CONFIG_SMP
|
||||
else if (irqnr < 16) {
|
||||
writel_relaxed(irqstat, gic_cpu_base_addr +
|
||||
GIC_CPU_EOI);
|
||||
handle_IPI(irqnr, regs);
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_LOCAL_TIMERS
|
||||
else if (irqnr == 29) {
|
||||
writel_relaxed(irqstat, gic_cpu_base_addr +
|
||||
GIC_CPU_EOI);
|
||||
handle_local_timer(regs);
|
||||
}
|
||||
#endif
|
||||
} while (1);
|
||||
}
|
||||
|
|
@ -13,6 +13,7 @@
|
|||
|
||||
struct platform_device;
|
||||
struct clk;
|
||||
enum mxc_cpu_pwr_mode;
|
||||
|
||||
extern void mx1_map_io(void);
|
||||
extern void mx21_map_io(void);
|
||||
|
|
@ -66,6 +67,7 @@ extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
|
|||
unsigned long ckih1, unsigned long ckih2);
|
||||
extern int mx51_clocks_init_dt(void);
|
||||
extern int mx53_clocks_init_dt(void);
|
||||
extern int mx6q_clocks_init(void);
|
||||
extern struct platform_device *mxc_register_gpio(char *name, int id,
|
||||
resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
|
||||
extern void mxc_set_cpu_type(unsigned int type);
|
||||
|
|
@ -88,6 +90,7 @@ extern void imx_print_silicon_rev(const char *cpu, int srev);
|
|||
|
||||
void avic_handle_irq(struct pt_regs *);
|
||||
void tzic_handle_irq(struct pt_regs *);
|
||||
void gic_handle_irq(struct pt_regs *);
|
||||
|
||||
#define imx1_handle_irq avic_handle_irq
|
||||
#define imx21_handle_irq avic_handle_irq
|
||||
|
|
@ -98,10 +101,36 @@ void tzic_handle_irq(struct pt_regs *);
|
|||
#define imx50_handle_irq tzic_handle_irq
|
||||
#define imx51_handle_irq tzic_handle_irq
|
||||
#define imx53_handle_irq tzic_handle_irq
|
||||
#define imx6q_handle_irq gic_handle_irq
|
||||
|
||||
extern void imx_enable_cpu(int cpu, bool enable);
|
||||
extern void imx_set_cpu_jump(int cpu, void *jump_addr);
|
||||
#ifdef CONFIG_DEBUG_LL
|
||||
extern void imx_lluart_map_io(void);
|
||||
#else
|
||||
static inline void imx_lluart_map_io(void) {}
|
||||
#endif
|
||||
extern void v7_cpu_resume(void);
|
||||
extern u32 *pl310_get_save_ptr(void);
|
||||
#ifdef CONFIG_SMP
|
||||
extern void v7_secondary_startup(void);
|
||||
extern void imx_scu_map_io(void);
|
||||
extern void imx_smp_prepare(void);
|
||||
#else
|
||||
static inline void imx_scu_map_io(void) {}
|
||||
static inline void imx_smp_prepare(void) {}
|
||||
#endif
|
||||
extern void imx_enable_cpu(int cpu, bool enable);
|
||||
extern void imx_set_cpu_jump(int cpu, void *jump_addr);
|
||||
extern void imx_src_init(void);
|
||||
extern void imx_gpc_init(void);
|
||||
extern void imx_gpc_pre_suspend(void);
|
||||
extern void imx_gpc_post_resume(void);
|
||||
extern void imx51_babbage_common_init(void);
|
||||
extern void imx53_ard_common_init(void);
|
||||
extern void imx53_evk_common_init(void);
|
||||
extern void imx53_qsb_common_init(void);
|
||||
extern void imx53_smd_common_init(void);
|
||||
extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
|
||||
extern void imx6q_pm_init(void);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -12,44 +12,20 @@
|
|||
*/
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#ifdef CONFIG_SOC_IMX1
|
||||
#ifdef CONFIG_DEBUG_IMX1_UART
|
||||
#define UART_PADDR MX1_UART1_BASE_ADDR
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_IMX25
|
||||
#ifdef UART_PADDR
|
||||
#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
|
||||
#endif
|
||||
#elif defined (CONFIG_DEBUG_IMX25_UART)
|
||||
#define UART_PADDR MX25_UART1_BASE_ADDR
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_IMX21) || defined (CONFIG_SOC_IMX27)
|
||||
#ifdef UART_PADDR
|
||||
#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
|
||||
#endif
|
||||
#elif defined (CONFIG_DEBUG_IMX21_IMX27_UART)
|
||||
#define UART_PADDR MX2x_UART1_BASE_ADDR
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_IMX31) || defined(CONFIG_SOC_IMX35)
|
||||
#ifdef UART_PADDR
|
||||
#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
|
||||
#endif
|
||||
#elif defined (CONFIG_DEBUG_IMX31_IMX35_UART)
|
||||
#define UART_PADDR MX3x_UART1_BASE_ADDR
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_IMX51
|
||||
#ifdef UART_PADDR
|
||||
#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
|
||||
#endif
|
||||
#elif defined (CONFIG_DEBUG_IMX51_UART)
|
||||
#define UART_PADDR MX51_UART1_BASE_ADDR
|
||||
#endif
|
||||
|
||||
/* iMX50/53 have same addresses, but not iMX51 */
|
||||
#if defined(CONFIG_SOC_IMX50) || defined(CONFIG_SOC_IMX53)
|
||||
#ifdef UART_PADDR
|
||||
#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
|
||||
#endif
|
||||
#elif defined (CONFIG_DEBUG_IMX50_IMX53_UART)
|
||||
#define UART_PADDR MX53_UART1_BASE_ADDR
|
||||
#elif defined (CONFIG_DEBUG_IMX6Q_UART)
|
||||
#define UART_PADDR MX6Q_UART4_BASE_ADDR
|
||||
#endif
|
||||
|
||||
#define UART_VADDR IMX_IO_ADDRESS(UART_PADDR)
|
||||
|
|
|
|||
|
|
@ -22,3 +22,9 @@
|
|||
|
||||
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
|
||||
.endm
|
||||
|
||||
.macro test_for_ipi, irqnr, irqstat, base, tmp
|
||||
.endm
|
||||
|
||||
.macro test_for_ltirq, irqnr, irqstat, base, tmp
|
||||
.endm
|
||||
|
|
|
|||
|
|
@ -91,6 +91,11 @@
|
|||
* SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
|
||||
* AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
|
||||
* AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
|
||||
* mx6q:
|
||||
* SCU 0x00a00000+0x001000 -> 0xf4000000+0x001000
|
||||
* CCM 0x020c4000+0x004000 -> 0xf42c4000+0x004000
|
||||
* ANATOP 0x020c8000+0x001000 -> 0xf42c8000+0x001000
|
||||
* UART4 0x021f0000+0x004000 -> 0xf42f0000+0x004000
|
||||
*/
|
||||
#define IMX_IO_P2V(x) ( \
|
||||
0xf4000000 + \
|
||||
|
|
@ -102,6 +107,7 @@
|
|||
|
||||
#include <mach/mxc.h>
|
||||
|
||||
#include <mach/mx6q.h>
|
||||
#include <mach/mx50.h>
|
||||
#include <mach/mx51.h>
|
||||
#include <mach/mx53.h>
|
||||
|
|
|
|||
|
|
@ -14,9 +14,15 @@
|
|||
#include <asm-generic/gpio.h>
|
||||
|
||||
/*
|
||||
* SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64
|
||||
* SoCs with GIC interrupt controller have 160 IRQs, those with TZIC
|
||||
* have 128 IRQs, and those with AVIC have 64.
|
||||
*
|
||||
* To support single image, the biggest number should be defined on
|
||||
* top of the list.
|
||||
*/
|
||||
#ifdef CONFIG_MXC_TZIC
|
||||
#if defined CONFIG_ARM_GIC
|
||||
#define MXC_INTERNAL_IRQS 160
|
||||
#elif defined CONFIG_MXC_TZIC
|
||||
#define MXC_INTERNAL_IRQS 128
|
||||
#else
|
||||
#define MXC_INTERNAL_IRQS 64
|
||||
|
|
|
|||
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#ifndef __MACH_MX6Q_H__
|
||||
#define __MACH_MX6Q_H__
|
||||
|
||||
#define MX6Q_IO_P2V(x) IMX_IO_P2V(x)
|
||||
#define MX6Q_IO_ADDRESS(x) IOMEM(MX6Q_IO_P2V(x))
|
||||
|
||||
/*
|
||||
* The following are the blocks that need to be statically mapped.
|
||||
* For other blocks, the base address really should be retrieved from
|
||||
* device tree.
|
||||
*/
|
||||
#define MX6Q_SCU_BASE_ADDR 0x00a00000
|
||||
#define MX6Q_SCU_SIZE 0x1000
|
||||
#define MX6Q_CCM_BASE_ADDR 0x020c4000
|
||||
#define MX6Q_CCM_SIZE 0x4000
|
||||
#define MX6Q_ANATOP_BASE_ADDR 0x020c8000
|
||||
#define MX6Q_ANATOP_SIZE 0x1000
|
||||
#define MX6Q_UART4_BASE_ADDR 0x021f0000
|
||||
#define MX6Q_UART4_SIZE 0x4000
|
||||
|
||||
#endif /* __MACH_MX6Q_H__ */
|
||||
|
|
@ -367,4 +367,11 @@ config SAMSUNG_PD
|
|||
help
|
||||
Say Y here if you want to control Power Domain by Runtime PM.
|
||||
|
||||
config DEBUG_S3C_UART
|
||||
depends on PLAT_SAMSUNG
|
||||
int
|
||||
default "0" if DEBUG_S3C_UART0
|
||||
default "1" if DEBUG_S3C_UART1
|
||||
default "2" if DEBUG_S3C_UART2
|
||||
|
||||
endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue