ARM: shmobile: r8a7740 dtsi: Add PM domain support
Add a device node for the System Controller, with subnodes that represent the hardware power area hierarchy. Hook up all devices to their respective PM domains. Add a minimal device node for the Coresight-ETM hardware block, and hook it up to the D4 PM domain, so the R-Mobile System Controller driver can keep the domain powered, until the new Coresight code handles runtime PM. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven
Simon Horman
parent
3b8df39034
commit
aba07789d8
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@ -25,6 +25,7 @@
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device_type = "cpu";
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reg = <0x0>;
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clock-frequency = <800000000>;
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power-domains = <&pd_a3sm>;
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};
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};
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@ -41,12 +42,18 @@
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interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
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};
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ptm {
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compatible = "arm,coresight-etm3x";
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power-domains = <&pd_d4>;
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};
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cmt1: timer@e6138000 {
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compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
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reg = <0xe6138000 0x170>;
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interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
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clock-names = "fck";
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power-domains = <&pd_c5>;
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renesas,channels-mask = <0x3f>;
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@ -72,6 +79,7 @@
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
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power-domains = <&pd_a4s>;
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};
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/* irqpin1: IRQ8 - IRQ15 */
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@ -93,6 +101,7 @@
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
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power-domains = <&pd_a4s>;
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};
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/* irqpin2: IRQ16 - IRQ23 */
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@ -114,6 +123,7 @@
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
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power-domains = <&pd_a4s>;
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};
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/* irqpin3: IRQ24 - IRQ31 */
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@ -135,6 +145,7 @@
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
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power-domains = <&pd_a4s>;
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};
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ether: ethernet@e9a00000 {
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@ -143,6 +154,7 @@
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<0xe9a01800 0x800>;
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interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
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power-domains = <&pd_a4s>;
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phy-mode = "mii";
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#address-cells = <1>;
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#size-cells = <0>;
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@ -159,6 +171,7 @@
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0 203 IRQ_TYPE_LEVEL_HIGH
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0 204 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
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power-domains = <&pd_a4r>;
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status = "disabled";
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};
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@ -172,6 +185,7 @@
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0 72 IRQ_TYPE_LEVEL_HIGH
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0 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -181,6 +195,7 @@
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interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -190,6 +205,7 @@
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interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -199,6 +215,7 @@
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interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -208,6 +225,7 @@
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interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -217,6 +235,7 @@
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interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -226,6 +245,7 @@
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interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -235,6 +255,7 @@
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interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -244,6 +265,7 @@
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interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -253,6 +275,7 @@
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interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
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clock-names = "sci_ick";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -271,12 +294,14 @@
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<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
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<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
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<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
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power-domains = <&pd_c5>;
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};
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tpu: pwm@e6600000 {
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compatible = "renesas,tpu-r8a7740", "renesas,tpu";
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reg = <0xe6600000 0x100>;
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clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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@ -287,6 +312,7 @@
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interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH
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0 57 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_MMC>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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@ -297,6 +323,7 @@
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0 118 IRQ_TYPE_LEVEL_HIGH
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0 119 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
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power-domains = <&pd_a3sp>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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@ -309,6 +336,7 @@
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0 122 IRQ_TYPE_LEVEL_HIGH
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0 123 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
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power-domains = <&pd_a3sp>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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@ -321,6 +349,7 @@
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0 126 IRQ_TYPE_LEVEL_HIGH
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0 127 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
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power-domains = <&pd_a3sp>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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@ -332,6 +361,7 @@
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reg = <0xfe1f0000 0x400>;
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interrupts = <0 9 0x4>;
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clocks = <&mstp3_clks R8A7740_CLK_FSI>;
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power-domains = <&pd_a4mp>;
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status = "disabled";
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};
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@ -343,6 +373,7 @@
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<0 200 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
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clock-names = "fck";
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power-domains = <&pd_a4r>;
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#renesas,channels = <3>;
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@ -357,6 +388,7 @@
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<0 172 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
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clock-names = "fck";
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power-domains = <&pd_a4r>;
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#renesas,channels = <3>;
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@ -543,4 +575,71 @@
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"usbhost", "sdhi2", "usbfunc", "usphy";
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};
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
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reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
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pm-domains {
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pd_c5: c5 {
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <0>;
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pd_a4lc: a4lc@1 {
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reg = <1>;
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#power-domain-cells = <0>;
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};
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pd_a4mp: a4mp@2 {
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reg = <2>;
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#power-domain-cells = <0>;
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};
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pd_d4: d4@3 {
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reg = <3>;
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#power-domain-cells = <0>;
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};
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pd_a4r: a4r@5 {
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reg = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <0>;
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pd_a3rv: a3rv@6 {
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reg = <6>;
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#power-domain-cells = <0>;
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};
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};
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pd_a4s: a4s@10 {
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reg = <10>;
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <0>;
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pd_a3sp: a3sp@11 {
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reg = <11>;
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#power-domain-cells = <0>;
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};
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pd_a3sm: a3sm@12 {
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reg = <12>;
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#power-domain-cells = <0>;
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};
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pd_a3sg: a3sg@13 {
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reg = <13>;
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#power-domain-cells = <0>;
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};
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};
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pd_a4su: a4su@20 {
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reg = <20>;
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#power-domain-cells = <0>;
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};
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};
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};
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};
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};
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