ARM: shmobile: r8a7740 dtsi: Add PM domain support

Add a device node for the System Controller, with subnodes that
represent the hardware power area hierarchy.
Hook up all devices to their respective PM domains.

Add a minimal device node for the Coresight-ETM hardware block, and hook
it up to the D4 PM domain, so the R-Mobile System Controller driver can
keep the domain powered, until the new Coresight code handles runtime
PM.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven 2014-12-03 14:41:46 +01:00 committed by Simon Horman
parent 3b8df39034
commit aba07789d8
1 changed files with 99 additions and 0 deletions

View File

@ -25,6 +25,7 @@
device_type = "cpu"; device_type = "cpu";
reg = <0x0>; reg = <0x0>;
clock-frequency = <800000000>; clock-frequency = <800000000>;
power-domains = <&pd_a3sm>;
}; };
}; };
@ -41,12 +42,18 @@
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
}; };
ptm {
compatible = "arm,coresight-etm3x";
power-domains = <&pd_d4>;
};
cmt1: timer@e6138000 { cmt1: timer@e6138000 {
compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48"; compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
reg = <0xe6138000 0x170>; reg = <0xe6138000 0x170>;
interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_CMT1>; clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
clock-names = "fck"; clock-names = "fck";
power-domains = <&pd_c5>;
renesas,channels-mask = <0x3f>; renesas,channels-mask = <0x3f>;
@ -72,6 +79,7 @@
0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH>; 0 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_INTCA>; clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
power-domains = <&pd_a4s>;
}; };
/* irqpin1: IRQ8 - IRQ15 */ /* irqpin1: IRQ8 - IRQ15 */
@ -93,6 +101,7 @@
0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH>; 0 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_INTCA>; clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
power-domains = <&pd_a4s>;
}; };
/* irqpin2: IRQ16 - IRQ23 */ /* irqpin2: IRQ16 - IRQ23 */
@ -114,6 +123,7 @@
0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH>; 0 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_INTCA>; clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
power-domains = <&pd_a4s>;
}; };
/* irqpin3: IRQ24 - IRQ31 */ /* irqpin3: IRQ24 - IRQ31 */
@ -135,6 +145,7 @@
0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH>; 0 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_INTCA>; clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
power-domains = <&pd_a4s>;
}; };
ether: ethernet@e9a00000 { ether: ethernet@e9a00000 {
@ -143,6 +154,7 @@
<0xe9a01800 0x800>; <0xe9a01800 0x800>;
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_GETHER>; clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
power-domains = <&pd_a4s>;
phy-mode = "mii"; phy-mode = "mii";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -159,6 +171,7 @@
0 203 IRQ_TYPE_LEVEL_HIGH 0 203 IRQ_TYPE_LEVEL_HIGH
0 204 IRQ_TYPE_LEVEL_HIGH>; 0 204 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7740_CLK_IIC0>; clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
power-domains = <&pd_a4r>;
status = "disabled"; status = "disabled";
}; };
@ -172,6 +185,7 @@
0 72 IRQ_TYPE_LEVEL_HIGH 0 72 IRQ_TYPE_LEVEL_HIGH
0 73 IRQ_TYPE_LEVEL_HIGH>; 0 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_IIC1>; clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
@ -181,6 +195,7 @@
interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>; clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
clock-names = "sci_ick"; clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
@ -190,6 +205,7 @@
interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>; clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
clock-names = "sci_ick"; clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
@ -199,6 +215,7 @@
interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>; clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
clock-names = "sci_ick"; clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
@ -208,6 +225,7 @@
interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>; clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
clock-names = "sci_ick"; clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
@ -217,6 +235,7 @@
interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>; clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
clock-names = "sci_ick"; clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
@ -226,6 +245,7 @@
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>; clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
clock-names = "sci_ick"; clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
@ -235,6 +255,7 @@
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>; clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
clock-names = "sci_ick"; clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
@ -244,6 +265,7 @@
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>; clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
clock-names = "sci_ick"; clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
@ -253,6 +275,7 @@
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
clock-names = "sci_ick"; clock-names = "sci_ick";
power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
@ -271,12 +294,14 @@
<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
power-domains = <&pd_c5>;
}; };
tpu: pwm@e6600000 { tpu: pwm@e6600000 {
compatible = "renesas,tpu-r8a7740", "renesas,tpu"; compatible = "renesas,tpu-r8a7740", "renesas,tpu";
reg = <0xe6600000 0x100>; reg = <0xe6600000 0x100>;
clocks = <&mstp3_clks R8A7740_CLK_TPU0>; clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
#pwm-cells = <3>; #pwm-cells = <3>;
}; };
@ -287,6 +312,7 @@
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH
0 57 IRQ_TYPE_LEVEL_HIGH>; 0 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_MMC>; clocks = <&mstp3_clks R8A7740_CLK_MMC>;
power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
@ -297,6 +323,7 @@
0 118 IRQ_TYPE_LEVEL_HIGH 0 118 IRQ_TYPE_LEVEL_HIGH
0 119 IRQ_TYPE_LEVEL_HIGH>; 0 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_SDHI0>; clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
power-domains = <&pd_a3sp>;
cap-sd-highspeed; cap-sd-highspeed;
cap-sdio-irq; cap-sdio-irq;
status = "disabled"; status = "disabled";
@ -309,6 +336,7 @@
0 122 IRQ_TYPE_LEVEL_HIGH 0 122 IRQ_TYPE_LEVEL_HIGH
0 123 IRQ_TYPE_LEVEL_HIGH>; 0 123 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_SDHI1>; clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
power-domains = <&pd_a3sp>;
cap-sd-highspeed; cap-sd-highspeed;
cap-sdio-irq; cap-sdio-irq;
status = "disabled"; status = "disabled";
@ -321,6 +349,7 @@
0 126 IRQ_TYPE_LEVEL_HIGH 0 126 IRQ_TYPE_LEVEL_HIGH
0 127 IRQ_TYPE_LEVEL_HIGH>; 0 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7740_CLK_SDHI2>; clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
power-domains = <&pd_a3sp>;
cap-sd-highspeed; cap-sd-highspeed;
cap-sdio-irq; cap-sdio-irq;
status = "disabled"; status = "disabled";
@ -332,6 +361,7 @@
reg = <0xfe1f0000 0x400>; reg = <0xfe1f0000 0x400>;
interrupts = <0 9 0x4>; interrupts = <0 9 0x4>;
clocks = <&mstp3_clks R8A7740_CLK_FSI>; clocks = <&mstp3_clks R8A7740_CLK_FSI>;
power-domains = <&pd_a4mp>;
status = "disabled"; status = "disabled";
}; };
@ -343,6 +373,7 @@
<0 200 IRQ_TYPE_LEVEL_HIGH>; <0 200 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7740_CLK_TMU0>; clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
clock-names = "fck"; clock-names = "fck";
power-domains = <&pd_a4r>;
#renesas,channels = <3>; #renesas,channels = <3>;
@ -357,6 +388,7 @@
<0 172 IRQ_TYPE_LEVEL_HIGH>; <0 172 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7740_CLK_TMU1>; clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
clock-names = "fck"; clock-names = "fck";
power-domains = <&pd_a4r>;
#renesas,channels = <3>; #renesas,channels = <3>;
@ -543,4 +575,71 @@
"usbhost", "sdhi2", "usbfunc", "usphy"; "usbhost", "sdhi2", "usbfunc", "usphy";
}; };
}; };
sysc: system-controller@e6180000 {
compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
pm-domains {
pd_c5: c5 {
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <0>;
pd_a4lc: a4lc@1 {
reg = <1>;
#power-domain-cells = <0>;
};
pd_a4mp: a4mp@2 {
reg = <2>;
#power-domain-cells = <0>;
};
pd_d4: d4@3 {
reg = <3>;
#power-domain-cells = <0>;
};
pd_a4r: a4r@5 {
reg = <5>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <0>;
pd_a3rv: a3rv@6 {
reg = <6>;
#power-domain-cells = <0>;
};
};
pd_a4s: a4s@10 {
reg = <10>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <0>;
pd_a3sp: a3sp@11 {
reg = <11>;
#power-domain-cells = <0>;
};
pd_a3sm: a3sm@12 {
reg = <12>;
#power-domain-cells = <0>;
};
pd_a3sg: a3sg@13 {
reg = <13>;
#power-domain-cells = <0>;
};
};
pd_a4su: a4su@20 {
reg = <20>;
#power-domain-cells = <0>;
};
};
};
};
}; };