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drm/amd/pm: Fix output of pp_od_clk_voltage 

Printing the other clock types should not be conditioned on being able
to print OD_SCLK. Some GPUs currently have limited capability of only
printing a subset of these.

Since this condition was introduced in v5.18-rc1, reading from
`pp_od_clk_voltage` has been returning empty on the Asus ROG Strix G15
(2021).

Fixes: 79c65f3fcb ("drm/amd/pm: do not expose power implementation details to amdgpu_pm.c")
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Jonatas Esteves <jntesteves@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jonatas Esteves 2023-05-20 10:39:52 -03:00 committed by Alex Deucher
parent a3ffabb250
commit ab22ecabe9
1 changed files with 5 additions and 7 deletions
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12
drivers/gpu/drm/amd/pm/amdgpu_pm.c
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@ -871,13 +871,11 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
}
if (ret == -ENOENT) {
size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
if (size > 0) {
size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size);
size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size);
size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size);
size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size);
size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size);
}
size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size);
size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size);
size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size);
size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size);
size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size);
}
if (size == 0)