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PMIC wrapper 

- support companion device
 - add support for MT6795
 
 SPMI:
 - add support for MT8186
 
 SVS:
 - change gpu node name to match binding
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Merge tag 'v6.4-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into soc/drivers

PMIC wrapper
- support companion device
- add support for MT6795

SPMI:
- add support for MT8186

SVS:
- change gpu node name to match binding

* tag 'v6.4-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
  soc: mediatek: SVS: Fix MT8192 GPU node name
  soc: mediatek: mtk-mutex: Remove unnecessary .owner
  dt-bindings: phy: mediatek,dsi-phy: Add compatible for MT6795 Helio X10
  dt-bindings: pwm: Add compatible for MediaTek MT6795
  dt-bindings: spmi: spmi-mtk-pmif: Document mediatek,mt8195-spmi as fallback of mediatek,mt8186-spmi
  soc: mediatek: pwrap: Add support for MT6795 Helio X10
  soc: mediatek: mtk-pmic-wrap: Add support for MT6331 w/ MT6332 companion
  soc: mediatek: mtk-pmic-wrap: Add support for companion PMICs
  soc: mediatek: pwrap: Add kerneldoc for struct pwrap_slv_type
  soc: mediatek: pwrap: Move PMIC read test sequence in function
  dt-bindings: soc: mediatek: pwrap: Add compatible for MT6795 Helio X10

Link: https://lore.kernel.org/r/1ed1e5ae-6305-e63a-84a0-3c43f69c8f8b@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-06-21 22:13:29 +02:00
parent a08000d5e0 21d4631eed
commit aaeb1b6367
8 changed files with 285 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
View File

@ -24,6 +24,10 @@ properties:
- enum:
- mediatek,mt7623-mipi-tx
- const: mediatek,mt2701-mipi-tx
- items:
- enum:
- mediatek,mt6795-mipi-tx
- const: mediatek,mt8173-mipi-tx
- items:
- enum:
- mediatek,mt8365-mipi-tx

4
Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
View File

@ -22,7 +22,9 @@ properties:
- mediatek,mt8173-disp-pwm
- mediatek,mt8183-disp-pwm
- items:
- const: mediatek,mt8167-disp-pwm
- enum:
- mediatek,mt6795-disp-pwm
- mediatek,mt8167-disp-pwm
- const: mediatek,mt8173-disp-pwm
- items:
- enum:

1
Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml
View File

@ -33,6 +33,7 @@ properties:
- mediatek,mt2701-pwrap
- mediatek,mt6765-pwrap
- mediatek,mt6779-pwrap
- mediatek,mt6795-pwrap
- mediatek,mt6797-pwrap
- mediatek,mt6873-pwrap
- mediatek,mt7622-pwrap

11
Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml
View File

@ -18,9 +18,14 @@ allOf:
properties:
compatible:
enum:
- mediatek,mt6873-spmi
- mediatek,mt8195-spmi
oneOf:
- enum:
- mediatek,mt6873-spmi
- mediatek,mt8195-spmi
- items:
- enum:
- mediatek,mt8186-spmi
- const: mediatek,mt8195-spmi
reg:
maxItems: 2

1
drivers/soc/mediatek/mtk-mutex.c
View File

@ -1051,7 +1051,6 @@ static struct platform_driver mtk_mutex_driver = {
.probe = mtk_mutex_probe,
.driver = {
.name = "mediatek-mutex",
.owner = THIS_MODULE,
.of_match_table = mutex_driver_dt_match,
},
};

292
drivers/soc/mediatek/mtk-pmic-wrap.c
View File

@ -47,6 +47,7 @@
/* macro for device wrapper default value */
#define PWRAP_DEW_READ_TEST_VAL 0x5aa5
#define PWRAP_DEW_COMP_READ_TEST_VAL 0xa55a
#define PWRAP_DEW_WRITE_TEST_VAL 0xa55a
/* macro for manual command */
@ -169,6 +170,40 @@ static const u32 mt6323_regs[] = {
[PWRAP_DEW_RDDMY_NO] = 0x01a4,
};
static const u32 mt6331_regs[] = {
[PWRAP_DEW_DIO_EN] = 0x018c,
[PWRAP_DEW_READ_TEST] = 0x018e,
[PWRAP_DEW_WRITE_TEST] = 0x0190,
[PWRAP_DEW_CRC_SWRST] = 0x0192,
[PWRAP_DEW_CRC_EN] = 0x0194,
[PWRAP_DEW_CRC_VAL] = 0x0196,
[PWRAP_DEW_MON_GRP_SEL] = 0x0198,
[PWRAP_DEW_CIPHER_KEY_SEL] = 0x019a,
[PWRAP_DEW_CIPHER_IV_SEL] = 0x019c,
[PWRAP_DEW_CIPHER_EN] = 0x019e,
[PWRAP_DEW_CIPHER_RDY] = 0x01a0,
[PWRAP_DEW_CIPHER_MODE] = 0x01a2,
[PWRAP_DEW_CIPHER_SWRST] = 0x01a4,
[PWRAP_DEW_RDDMY_NO] = 0x01a6,
};
static const u32 mt6332_regs[] = {
[PWRAP_DEW_DIO_EN] = 0x80f6,
[PWRAP_DEW_READ_TEST] = 0x80f8,
[PWRAP_DEW_WRITE_TEST] = 0x80fa,
[PWRAP_DEW_CRC_SWRST] = 0x80fc,
[PWRAP_DEW_CRC_EN] = 0x80fe,
[PWRAP_DEW_CRC_VAL] = 0x8100,
[PWRAP_DEW_MON_GRP_SEL] = 0x8102,
[PWRAP_DEW_CIPHER_KEY_SEL] = 0x8104,
[PWRAP_DEW_CIPHER_IV_SEL] = 0x8106,
[PWRAP_DEW_CIPHER_EN] = 0x8108,
[PWRAP_DEW_CIPHER_RDY] = 0x810a,
[PWRAP_DEW_CIPHER_MODE] = 0x810c,
[PWRAP_DEW_CIPHER_SWRST] = 0x810e,
[PWRAP_DEW_RDDMY_NO] = 0x8110,
};
static const u32 mt6351_regs[] = {
[PWRAP_DEW_DIO_EN] = 0x02F2,
[PWRAP_DEW_READ_TEST] = 0x02F4,
@ -604,6 +639,91 @@ static int mt6779_regs[] = {
[PWRAP_WACS2_VLDCLR] = 0xC28,
};
static int mt6795_regs[] = {
[PWRAP_MUX_SEL] = 0x0,
[PWRAP_WRAP_EN] = 0x4,
[PWRAP_DIO_EN] = 0x8,
[PWRAP_SIDLY] = 0xc,
[PWRAP_RDDMY] = 0x10,
[PWRAP_SI_CK_CON] = 0x14,
[PWRAP_CSHEXT_WRITE] = 0x18,
[PWRAP_CSHEXT_READ] = 0x1c,
[PWRAP_CSLEXT_START] = 0x20,
[PWRAP_CSLEXT_END] = 0x24,
[PWRAP_STAUPD_PRD] = 0x28,
[PWRAP_STAUPD_GRPEN] = 0x2c,
[PWRAP_EINT_STA0_ADR] = 0x30,
[PWRAP_EINT_STA1_ADR] = 0x34,
[PWRAP_STAUPD_MAN_TRIG] = 0x40,
[PWRAP_STAUPD_STA] = 0x44,
[PWRAP_WRAP_STA] = 0x48,
[PWRAP_HARB_INIT] = 0x4c,
[PWRAP_HARB_HPRIO] = 0x50,
[PWRAP_HIPRIO_ARB_EN] = 0x54,
[PWRAP_HARB_STA0] = 0x58,
[PWRAP_HARB_STA1] = 0x5c,
[PWRAP_MAN_EN] = 0x60,
[PWRAP_MAN_CMD] = 0x64,
[PWRAP_MAN_RDATA] = 0x68,
[PWRAP_MAN_VLDCLR] = 0x6c,
[PWRAP_WACS0_EN] = 0x70,
[PWRAP_INIT_DONE0] = 0x74,
[PWRAP_WACS0_CMD] = 0x78,
[PWRAP_WACS0_RDATA] = 0x7c,
[PWRAP_WACS0_VLDCLR] = 0x80,
[PWRAP_WACS1_EN] = 0x84,
[PWRAP_INIT_DONE1] = 0x88,
[PWRAP_WACS1_CMD] = 0x8c,
[PWRAP_WACS1_RDATA] = 0x90,
[PWRAP_WACS1_VLDCLR] = 0x94,
[PWRAP_WACS2_EN] = 0x98,
[PWRAP_INIT_DONE2] = 0x9c,
[PWRAP_WACS2_CMD] = 0xa0,
[PWRAP_WACS2_RDATA] = 0xa4,
[PWRAP_WACS2_VLDCLR] = 0xa8,
[PWRAP_INT_EN] = 0xac,
[PWRAP_INT_FLG_RAW] = 0xb0,
[PWRAP_INT_FLG] = 0xb4,
[PWRAP_INT_CLR] = 0xb8,
[PWRAP_SIG_ADR] = 0xbc,
[PWRAP_SIG_MODE] = 0xc0,
[PWRAP_SIG_VALUE] = 0xc4,
[PWRAP_SIG_ERRVAL] = 0xc8,
[PWRAP_CRC_EN] = 0xcc,
[PWRAP_TIMER_EN] = 0xd0,
[PWRAP_TIMER_STA] = 0xd4,
[PWRAP_WDT_UNIT] = 0xd8,
[PWRAP_WDT_SRC_EN] = 0xdc,
[PWRAP_WDT_FLG] = 0xe0,
[PWRAP_DEBUG_INT_SEL] = 0xe4,
[PWRAP_DVFS_ADR0] = 0xe8,
[PWRAP_DVFS_WDATA0] = 0xec,
[PWRAP_DVFS_ADR1] = 0xf0,
[PWRAP_DVFS_WDATA1] = 0xf4,
[PWRAP_DVFS_ADR2] = 0xf8,
[PWRAP_DVFS_WDATA2] = 0xfc,
[PWRAP_DVFS_ADR3] = 0x100,
[PWRAP_DVFS_WDATA3] = 0x104,
[PWRAP_DVFS_ADR4] = 0x108,
[PWRAP_DVFS_WDATA4] = 0x10c,
[PWRAP_DVFS_ADR5] = 0x110,
[PWRAP_DVFS_WDATA5] = 0x114,
[PWRAP_DVFS_ADR6] = 0x118,
[PWRAP_DVFS_WDATA6] = 0x11c,
[PWRAP_DVFS_ADR7] = 0x120,
[PWRAP_DVFS_WDATA7] = 0x124,
[PWRAP_SPMINF_STA] = 0x128,
[PWRAP_CIPHER_KEY_SEL] = 0x12c,
[PWRAP_CIPHER_IV_SEL] = 0x130,
[PWRAP_CIPHER_EN] = 0x134,
[PWRAP_CIPHER_RDY] = 0x138,
[PWRAP_CIPHER_MODE] = 0x13c,
[PWRAP_CIPHER_SWRST] = 0x140,
[PWRAP_DCM_EN] = 0x144,
[PWRAP_DCM_DBC_PRD] = 0x148,
[PWRAP_EXT_CK] = 0x14c,
};
static int mt6797_regs[] = {
[PWRAP_MUX_SEL] = 0x0,
[PWRAP_WRAP_EN] = 0x4,
@ -1181,6 +1301,8 @@ static int mt8186_regs[] = {
enum pmic_type {
PMIC_MT6323,
PMIC_MT6331,
PMIC_MT6332,
PMIC_MT6351,
PMIC_MT6357,
PMIC_MT6358,
@ -1193,6 +1315,7 @@ enum pwrap_type {
PWRAP_MT2701,
PWRAP_MT6765,
PWRAP_MT6779,
PWRAP_MT6795,
PWRAP_MT6797,
PWRAP_MT6873,
PWRAP_MT7622,
@ -1218,11 +1341,21 @@ struct pwrap_slv_regops {
int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata);
};
/**
* struct pwrap_slv_type - PMIC device wrapper definitions
* @dew_regs: Device Wrapper (DeW) register offsets
* @type: PMIC Type (model)
* @comp_dew_regs: Device Wrapper (DeW) register offsets for companion device
* @comp_type: Companion PMIC Type (model)
* @regops: Register R/W ops
* @caps: Capability flags for the target device
*/
struct pwrap_slv_type {
const u32 *dew_regs;
enum pmic_type type;
const u32 *comp_dew_regs;
enum pmic_type comp_type;
const struct pwrap_slv_regops *regops;
/* Flags indicating the capability for the target slave */
u32 caps;
};
@ -1455,6 +1588,18 @@ static int pwrap_regmap_write(void *context, u32 adr, u32 wdata)
return pwrap_write(context, adr, wdata);
}
static bool pwrap_pmic_read_test(struct pmic_wrapper *wrp, const u32 *dew_regs,
u16 read_test_val)
{
bool is_success;
u32 rdata;
pwrap_read(wrp, dew_regs[PWRAP_DEW_READ_TEST], &rdata);
is_success = ((rdata & U16_MAX) == read_test_val);
return is_success;
}
static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
{
bool tmp;
@ -1498,18 +1643,18 @@ static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
*/
static int pwrap_init_sidly(struct pmic_wrapper *wrp)
{
u32 rdata;
u32 i;
u32 pass = 0;
bool read_ok;
signed char dly[16] = {
-1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1
};
for (i = 0; i < 4; i++) {
pwrap_writel(wrp, i, PWRAP_SIDLY);
pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST],
&rdata);
if (rdata == PWRAP_DEW_READ_TEST_VAL) {
read_ok = pwrap_pmic_read_test(wrp, wrp->slave->dew_regs,
PWRAP_DEW_READ_TEST_VAL);
if (read_ok) {
dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
pass |= 1 << i;
}
@ -1529,11 +1674,13 @@ static int pwrap_init_sidly(struct pmic_wrapper *wrp)
static int pwrap_init_dual_io(struct pmic_wrapper *wrp)
{
int ret;
bool tmp;
u32 rdata;
bool read_ok, tmp;
bool comp_read_ok = true;
/* Enable dual IO mode */
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
if (wrp->slave->comp_dew_regs)
pwrap_write(wrp, wrp->slave->comp_dew_regs[PWRAP_DEW_DIO_EN], 1);
/* Check IDLE & INIT_DONE in advance */
ret = readx_poll_timeout(pwrap_is_fsm_idle_and_sync_idle, wrp, tmp, tmp,
@ -1546,12 +1693,15 @@ static int pwrap_init_dual_io(struct pmic_wrapper *wrp)
pwrap_writel(wrp, 1, PWRAP_DIO_EN);
/* Read Test */
pwrap_read(wrp,
wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
if (rdata != PWRAP_DEW_READ_TEST_VAL) {
dev_err(wrp->dev,
"Read failed on DIO mode: 0x%04x!=0x%04x\n",
PWRAP_DEW_READ_TEST_VAL, rdata);
read_ok = pwrap_pmic_read_test(wrp, wrp->slave->dew_regs, PWRAP_DEW_READ_TEST_VAL);
if (wrp->slave->comp_dew_regs)
comp_read_ok = pwrap_pmic_read_test(wrp, wrp->slave->comp_dew_regs,
PWRAP_DEW_COMP_READ_TEST_VAL);
if (!read_ok || !comp_read_ok) {
dev_err(wrp->dev, "Read failed on DIO mode. Main PMIC %s%s\n",
!read_ok ? "fail" : "success",
wrp->slave->comp_dew_regs && !comp_read_ok ?
", Companion PMIC fail" : "");
return -EFAULT;
}
@ -1586,6 +1736,20 @@ static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,
static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)
{
switch (wrp->master->type) {
case PWRAP_MT6795:
if (wrp->slave->type == PMIC_MT6331) {
const u32 *dew_regs = wrp->slave->dew_regs;
pwrap_write(wrp, dew_regs[PWRAP_DEW_RDDMY_NO], 0x8);
if (wrp->slave->comp_type == PMIC_MT6332) {
dew_regs = wrp->slave->comp_dew_regs;
pwrap_write(wrp, dew_regs[PWRAP_DEW_RDDMY_NO], 0x8);
}
}
pwrap_writel(wrp, 0x88, PWRAP_RDDMY);
pwrap_init_chip_select_ext(wrp, 15, 15, 15, 15);
break;
case PWRAP_MT8173:
pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2);
break;
@ -1626,19 +1790,41 @@ static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
}
static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
static bool __pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp, const u32 *dew_regs)
{
u32 rdata;
int ret;
ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY],
&rdata);
ret = pwrap_read(wrp, dew_regs[PWRAP_DEW_CIPHER_RDY], &rdata);
if (ret)
return false;
return rdata == 1;
}
static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
{
bool ret = __pwrap_is_pmic_cipher_ready(wrp, wrp->slave->dew_regs);
if (!ret)
return ret;
/* If there's any companion, wait for it to be ready too */
if (wrp->slave->comp_dew_regs)
ret = __pwrap_is_pmic_cipher_ready(wrp, wrp->slave->comp_dew_regs);
return ret;
}
static void pwrap_config_cipher(struct pmic_wrapper *wrp, const u32 *dew_regs)
{
pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1);
pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0);
pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1);
pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2);
}
static int pwrap_init_cipher(struct pmic_wrapper *wrp)
{
int ret;
@ -1658,6 +1844,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
case PWRAP_MT2701:
case PWRAP_MT6765:
case PWRAP_MT6779:
case PWRAP_MT6795:
case PWRAP_MT6797:
case PWRAP_MT8173:
case PWRAP_MT8186:
@ -1675,10 +1862,11 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
}
/* Config cipher mode @PMIC */
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1);
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0);
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1);
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2);
pwrap_config_cipher(wrp, wrp->slave->dew_regs);
/* If there is any companion PMIC, configure cipher mode there too */
if (wrp->slave->comp_type > 0)
pwrap_config_cipher(wrp, wrp->slave->comp_dew_regs);
switch (wrp->slave->type) {
case PMIC_MT6397:
@ -1740,6 +1928,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
static int pwrap_init_security(struct pmic_wrapper *wrp)
{
u32 crc_val;
int ret;
/* Enable encryption */
@ -1748,14 +1937,21 @@ static int pwrap_init_security(struct pmic_wrapper *wrp)
return ret;
/* Signature checking - using CRC */
if (pwrap_write(wrp,
wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
return -EFAULT;
ret = pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1);
if (ret == 0 && wrp->slave->comp_dew_regs)
ret = pwrap_write(wrp, wrp->slave->comp_dew_regs[PWRAP_DEW_CRC_EN], 0x1);
pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
PWRAP_SIG_ADR);
/* CRC value */
crc_val = wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL];
if (wrp->slave->comp_dew_regs)
crc_val |= wrp->slave->comp_dew_regs[PWRAP_DEW_CRC_VAL] << 16;
pwrap_writel(wrp, crc_val, PWRAP_SIG_ADR);
/* PMIC Wrapper Arbiter priority */
pwrap_writel(wrp,
wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
@ -1819,6 +2015,19 @@ static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)
return 0;
}
static int pwrap_mt6795_init_soc_specific(struct pmic_wrapper *wrp)
{
pwrap_writel(wrp, 0xf, PWRAP_STAUPD_GRPEN);
if (wrp->slave->type == PMIC_MT6331)
pwrap_writel(wrp, 0x1b4, PWRAP_EINT_STA0_ADR);
if (wrp->slave->comp_type == PMIC_MT6332)
pwrap_writel(wrp, 0x8112, PWRAP_EINT_STA1_ADR);
return 0;
}
static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
{
pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD);
@ -1854,10 +2063,16 @@ static int pwrap_init(struct pmic_wrapper *wrp)
if (wrp->rstc_bridge)
reset_control_reset(wrp->rstc_bridge);
if (wrp->master->type == PWRAP_MT8173) {
switch (wrp->master->type) {
case PWRAP_MT6795:
fallthrough;
case PWRAP_MT8173:
/* Enable DCM */
pwrap_writel(wrp, 3, PWRAP_DCM_EN);
pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
break;
default:
break;
}
if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
@ -1982,6 +2197,16 @@ static const struct pwrap_slv_type pmic_mt6323 = {
PWRAP_SLV_CAP_SECURITY,
};
static const struct pwrap_slv_type pmic_mt6331 = {
.dew_regs = mt6331_regs,
.type = PMIC_MT6331,
.comp_dew_regs = mt6332_regs,
.comp_type = PMIC_MT6332,
.regops = &pwrap_regops16,
.caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
PWRAP_SLV_CAP_SECURITY,
};
static const struct pwrap_slv_type pmic_mt6351 = {
.dew_regs = mt6351_regs,
.type = PMIC_MT6351,
@ -2027,6 +2252,7 @@ static const struct pwrap_slv_type pmic_mt6397 = {
static const struct of_device_id of_slave_match_tbl[] = {
{ .compatible = "mediatek,mt6323", .data = &pmic_mt6323 },
{ .compatible = "mediatek,mt6331", .data = &pmic_mt6331 },
{ .compatible = "mediatek,mt6351", .data = &pmic_mt6351 },
{ .compatible = "mediatek,mt6357", .data = &pmic_mt6357 },
{ .compatible = "mediatek,mt6358", .data = &pmic_mt6358 },
@ -2079,6 +2305,19 @@ static const struct pmic_wrapper_type pwrap_mt6779 = {
.init_soc_specific = NULL,
};
static const struct pmic_wrapper_type pwrap_mt6795 = {
.regs = mt6795_regs,
.type = PWRAP_MT6795,
.arb_en_all = 0x3f,
.int_en_all = ~(u32)(BIT(31) | BIT(2) | BIT(1)),
.int1_en_all = 0,
.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
.wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
.caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
.init_reg_clock = pwrap_common_init_reg_clock,
.init_soc_specific = pwrap_mt6795_init_soc_specific,
};
static const struct pmic_wrapper_type pwrap_mt6797 = {
.regs = mt6797_regs,
.type = PWRAP_MT6797,
@ -2212,6 +2451,7 @@ static const struct of_device_id of_pwrap_match_tbl[] = {
{ .compatible = "mediatek,mt2701-pwrap", .data = &pwrap_mt2701 },
{ .compatible = "mediatek,mt6765-pwrap", .data = &pwrap_mt6765 },
{ .compatible = "mediatek,mt6779-pwrap", .data = &pwrap_mt6779 },
{ .compatible = "mediatek,mt6795-pwrap", .data = &pwrap_mt6795 },
{ .compatible = "mediatek,mt6797-pwrap", .data = &pwrap_mt6797 },
{ .compatible = "mediatek,mt6873-pwrap", .data = &pwrap_mt6873 },
{ .compatible = "mediatek,mt7622-pwrap", .data = &pwrap_mt7622 },

4
drivers/soc/mediatek/mtk-svs.c
View File

@ -2061,9 +2061,9 @@ static int svs_mt8192_platform_probe(struct svs_platform *svsp)
svsb = &svsp->banks[idx];
if (svsb->type == SVSB_HIGH)
svsb->opp_dev = svs_add_device_link(svsp, "mali");
svsb->opp_dev = svs_add_device_link(svsp, "gpu");
else if (svsb->type == SVSB_LOW)
svsb->opp_dev = svs_get_subsys_device(svsp, "mali");
svsb->opp_dev = svs_get_subsys_device(svsp, "gpu");
if (IS_ERR(svsb->opp_dev))
return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev),

3
include/linux/soc/mediatek/mtk-mmsys.h
View File

@ -27,8 +27,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_CCORR,
DDP_COMPONENT_COLOR0,
DDP_COMPONENT_COLOR1,
DDP_COMPONENT_DITHER,
DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
DDP_COMPONENT_DITHER0,
DDP_COMPONENT_DITHER1,
DDP_COMPONENT_DP_INTF0,
DDP_COMPONENT_DP_INTF1,