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net: fman: dtsec: Always gracefully stop/start 

There are two ways that GRS can be set: graceful_stop and dtsec_isr. It
is cleared by graceful_start. If it is already set before calling
graceful_stop, then that means that dtsec_isr set it. In that case, we
will not set GRS nor will we clear it (which seems like a bug?). For GTS
the logic is similar, except that there is no one else messing with this
bit (so we will always set and clear it). Simplify the logic by always
setting/clearing GRS/GTS. This is less racy that the previous behavior,
and ensures that we always end up clearing the bits. This can of course
clear GRS while dtsec_isr is waiting, but because we have already done
our own waiting it should be fine.

This is the last user of enum comm_mode, so remove it.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Acked-by: Camelia Groza <camelia.groza@nxp.com>
Tested-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Sean Anderson 2022-08-18 12:16:29 -04:00 committed by Jakub Kicinski
parent e61406a195
commit aae73fde7e
2 changed files with 30 additions and 74 deletions
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94
drivers/net/ethernet/freescale/fman/fman_dtsec.c
View File

@ -833,49 +833,41 @@ int dtsec_cfg_pad_and_crc(struct fman_mac *dtsec, bool new_val)
return 0;
}
static void graceful_start(struct fman_mac *dtsec, enum comm_mode mode)
static void graceful_start(struct fman_mac *dtsec)
{
struct dtsec_regs __iomem *regs = dtsec->regs;
if (mode & COMM_MODE_TX)
iowrite32be(ioread32be(&regs->tctrl) &
~TCTRL_GTS, &regs->tctrl);
if (mode & COMM_MODE_RX)
iowrite32be(ioread32be(&regs->rctrl) &
~RCTRL_GRS, &regs->rctrl);
iowrite32be(ioread32be(&regs->tctrl) & ~TCTRL_GTS, &regs->tctrl);
iowrite32be(ioread32be(&regs->rctrl) & ~RCTRL_GRS, &regs->rctrl);
}
static void graceful_stop(struct fman_mac *dtsec, enum comm_mode mode)
static void graceful_stop(struct fman_mac *dtsec)
{
struct dtsec_regs __iomem *regs = dtsec->regs;
u32 tmp;
/* Graceful stop - Assert the graceful Rx stop bit */
if (mode & COMM_MODE_RX) {
tmp = ioread32be(&regs->rctrl) | RCTRL_GRS;
iowrite32be(tmp, &regs->rctrl);
tmp = ioread32be(&regs->rctrl) | RCTRL_GRS;
iowrite32be(tmp, &regs->rctrl);
if (dtsec->fm_rev_info.major == 2) {
/* Workaround for dTSEC Errata A002 */
usleep_range(100, 200);
} else {
/* Workaround for dTSEC Errata A004839 */
usleep_range(10, 50);
}
if (dtsec->fm_rev_info.major == 2) {
/* Workaround for dTSEC Errata A002 */
usleep_range(100, 200);
} else {
/* Workaround for dTSEC Errata A004839 */
usleep_range(10, 50);
}
/* Graceful stop - Assert the graceful Tx stop bit */
if (mode & COMM_MODE_TX) {
if (dtsec->fm_rev_info.major == 2) {
/* dTSEC Errata A004: Do not use TCTRL[GTS]=1 */
pr_debug("GTS not supported due to DTSEC_A004 Errata.\n");
} else {
tmp = ioread32be(&regs->tctrl) | TCTRL_GTS;
iowrite32be(tmp, &regs->tctrl);
if (dtsec->fm_rev_info.major == 2) {
/* dTSEC Errata A004: Do not use TCTRL[GTS]=1 */
pr_debug("GTS not supported due to DTSEC_A004 Errata.\n");
} else {
tmp = ioread32be(&regs->tctrl) | TCTRL_GTS;
iowrite32be(tmp, &regs->tctrl);
/* Workaround for dTSEC Errata A0012, A0014 */
usleep_range(10, 50);
}
/* Workaround for dTSEC Errata A0012, A0014 */
usleep_range(10, 50);
}
}
@ -893,7 +885,7 @@ int dtsec_enable(struct fman_mac *dtsec)
iowrite32be(tmp, &regs->maccfg1);
/* Graceful start - clear the graceful Rx/Tx stop bit */
graceful_start(dtsec, COMM_MODE_RX_AND_TX);
graceful_start(dtsec);
return 0;
}
@ -907,7 +899,7 @@ int dtsec_disable(struct fman_mac *dtsec)
return -EINVAL;
/* Graceful stop - Assert the graceful Rx/Tx stop bit */
graceful_stop(dtsec, COMM_MODE_RX_AND_TX);
graceful_stop(dtsec);
tmp = ioread32be(&regs->maccfg1);
tmp &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
@ -921,18 +913,12 @@ int dtsec_set_tx_pause_frames(struct fman_mac *dtsec,
u16 pause_time, u16 __maybe_unused thresh_time)
{
struct dtsec_regs __iomem *regs = dtsec->regs;
enum comm_mode mode = COMM_MODE_NONE;
u32 ptv = 0;
if (!is_init_done(dtsec->dtsec_drv_param))
return -EINVAL;
if ((ioread32be(&regs->rctrl) & RCTRL_GRS) == 0)
mode |= COMM_MODE_RX;
if ((ioread32be(&regs->tctrl) & TCTRL_GTS) == 0)
mode |= COMM_MODE_TX;
graceful_stop(dtsec, mode);
graceful_stop(dtsec);
if (pause_time) {
/* FM_BAD_TX_TS_IN_B_2_B_ERRATA_DTSEC_A003 Errata workaround */
@ -954,7 +940,7 @@ int dtsec_set_tx_pause_frames(struct fman_mac *dtsec,
iowrite32be(ioread32be(&regs->maccfg1) & ~MACCFG1_TX_FLOW,
&regs->maccfg1);
graceful_start(dtsec, mode);
graceful_start(dtsec);
return 0;
}
@ -962,18 +948,12 @@ int dtsec_set_tx_pause_frames(struct fman_mac *dtsec,
int dtsec_accept_rx_pause_frames(struct fman_mac *dtsec, bool en)
{
struct dtsec_regs __iomem *regs = dtsec->regs;
enum comm_mode mode = COMM_MODE_NONE;
u32 tmp;
if (!is_init_done(dtsec->dtsec_drv_param))
return -EINVAL;
if ((ioread32be(&regs->rctrl) & RCTRL_GRS) == 0)
mode |= COMM_MODE_RX;
if ((ioread32be(&regs->tctrl) & TCTRL_GTS) == 0)
mode |= COMM_MODE_TX;
graceful_stop(dtsec, mode);
graceful_stop(dtsec);
tmp = ioread32be(&regs->maccfg1);
if (en)
@ -982,25 +962,17 @@ int dtsec_accept_rx_pause_frames(struct fman_mac *dtsec, bool en)
tmp &= ~MACCFG1_RX_FLOW;
iowrite32be(tmp, &regs->maccfg1);
graceful_start(dtsec, mode);
graceful_start(dtsec);
return 0;
}
int dtsec_modify_mac_address(struct fman_mac *dtsec, const enet_addr_t *enet_addr)
{
struct dtsec_regs __iomem *regs = dtsec->regs;
enum comm_mode mode = COMM_MODE_NONE;
if (!is_init_done(dtsec->dtsec_drv_param))
return -EINVAL;
if ((ioread32be(&regs->rctrl) & RCTRL_GRS) == 0)
mode |= COMM_MODE_RX;
if ((ioread32be(&regs->tctrl) & TCTRL_GTS) == 0)
mode |= COMM_MODE_TX;
graceful_stop(dtsec, mode);
graceful_stop(dtsec);
/* Initialize MAC Station Address registers (1 & 2)
* Station address have to be swapped (big endian to little endian
@ -1008,7 +980,7 @@ int dtsec_modify_mac_address(struct fman_mac *dtsec, const enet_addr_t *enet_add
dtsec->addr = ENET_ADDR_TO_UINT64(*enet_addr);
set_mac_address(dtsec->regs, (const u8 *)(*enet_addr));
graceful_start(dtsec, mode);
graceful_start(dtsec);
return 0;
}
@ -1226,18 +1198,12 @@ int dtsec_set_promiscuous(struct fman_mac *dtsec, bool new_val)
int dtsec_adjust_link(struct fman_mac *dtsec, u16 speed)
{
struct dtsec_regs __iomem *regs = dtsec->regs;
enum comm_mode mode = COMM_MODE_NONE;
u32 tmp;
if (!is_init_done(dtsec->dtsec_drv_param))
return -EINVAL;
if ((ioread32be(&regs->rctrl) & RCTRL_GRS) == 0)
mode |= COMM_MODE_RX;
if ((ioread32be(&regs->tctrl) & TCTRL_GTS) == 0)
mode |= COMM_MODE_TX;
graceful_stop(dtsec, mode);
graceful_stop(dtsec);
tmp = ioread32be(&regs->maccfg2);
@ -1258,7 +1224,7 @@ int dtsec_adjust_link(struct fman_mac *dtsec, u16 speed)
tmp &= ~DTSEC_ECNTRL_R100M;
iowrite32be(tmp, &regs->ecntrl);
graceful_start(dtsec, mode);
graceful_start(dtsec);
return 0;
}

10
drivers/net/ethernet/freescale/fman/fman_mac.h
View File

@ -75,16 +75,6 @@ typedef u8 enet_addr_t[ETH_ALEN];
#define ETH_HASH_ENTRY_OBJ(ptr) \
hlist_entry_safe(ptr, struct eth_hash_entry, node)
/* Enumeration (bit flags) of communication modes (Transmit,
* receive or both).
*/
enum comm_mode {
COMM_MODE_NONE = 0, /* No transmit/receive communication */
COMM_MODE_RX = 1, /* Only receive communication */
COMM_MODE_TX = 2, /* Only transmit communication */
COMM_MODE_RX_AND_TX = 3 /* Both transmit and receive communication */
};
/* FM MAC Exceptions */
enum fman_mac_exceptions {
FM_MAC_EX_10G_MDIO_SCAN_EVENT = 0