net: dsa: bcm_sf2: communicate integrated PHY revision to PHY driver
The integrated BCM7xxx PHY contains no useful revision information in its MII_PHYSID2 bits 3:0, that information is instead contained in the SWITCH_REG_PHY_REVISION register. Read this register, store its value, and return it by implementing the dsa_switch::get_phy_flags() callback accordingly. The register layout is already matching what the BCM7xxx PHY driver is expecting to find. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -376,6 +376,9 @@ static int bcm_sf2_sw_setup(struct dsa_switch *ds)
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SWITCH_TOP_REV_MASK;
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priv->hw_params.core_rev = (rev & SF2_REV_MASK);
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rev = reg_readl(priv, REG_PHY_REVISION);
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priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
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pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
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priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
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priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
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@ -399,6 +402,18 @@ static int bcm_sf2_sw_set_addr(struct dsa_switch *ds, u8 *addr)
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return 0;
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}
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static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
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{
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struct bcm_sf2_priv *priv = ds_to_priv(ds);
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/* The BCM7xxx PHY driver expects to find the integrated PHY revision
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* in bits 15:8 and the patch level in bits 7:0 which is exactly what
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* the REG_PHY_REVISION register layout is.
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*/
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return priv->hw_params.gphy_rev;
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}
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static int bcm_sf2_sw_indir_rw(struct dsa_switch *ds, int op, int addr,
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int regnum, u16 val)
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{
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@ -597,6 +612,7 @@ static struct dsa_switch_driver bcm_sf2_switch_driver = {
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.probe = bcm_sf2_sw_probe,
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.setup = bcm_sf2_sw_setup,
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.set_addr = bcm_sf2_sw_set_addr,
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.get_phy_flags = bcm_sf2_sw_get_phy_flags,
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.phy_read = bcm_sf2_sw_phy_read,
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.phy_write = bcm_sf2_sw_phy_write,
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.get_strings = bcm_sf2_sw_get_strings,
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@ -26,6 +26,7 @@
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struct bcm_sf2_hw_params {
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u16 top_rev;
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u16 core_rev;
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u16 gphy_rev;
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u32 num_gphy;
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u8 num_acb_queue;
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u8 num_rgmii;
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@ -25,6 +25,7 @@
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#define SWITCH_TOP_REV_MASK 0xffff
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#define REG_PHY_REVISION 0x1C
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#define PHY_REVISION_MASK 0xffff
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#define REG_SPHY_CNTRL 0x2C
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#define IDDQ_BIAS (1 << 0)
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