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i.MX51: handle IRQ for gpio 16..31 

The i.MX51 generates 2 IRQ for each GPIO bank : one for gpio 0 to 15
and one for gpio 16 to 31.
Actually only the lower IRQ is registered so register the second one.

Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Eric Bénard 2010-07-21 14:46:11 +02:00 committed by Sascha Hauer
parent 5055d1efc0
commit aa87214319
3 changed files with 11 additions and 0 deletions
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4
arch/arm/mach-mx5/devices.c
View File

@ -250,24 +250,28 @@ static struct mxc_gpio_port mxc_gpio_ports[] = {
.chip.label = "gpio-0",
.base = MX51_IO_ADDRESS(MX51_GPIO1_BASE_ADDR),
.irq = MX51_MXC_INT_GPIO1_LOW,
.irq_high = MX51_MXC_INT_GPIO1_HIGH,
.virtual_irq_start = MXC_GPIO_IRQ_START
},
{
.chip.label = "gpio-1",
.base = MX51_IO_ADDRESS(MX51_GPIO2_BASE_ADDR),
.irq = MX51_MXC_INT_GPIO2_LOW,
.irq_high = MX51_MXC_INT_GPIO2_HIGH,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 1
},
{
.chip.label = "gpio-2",
.base = MX51_IO_ADDRESS(MX51_GPIO3_BASE_ADDR),
.irq = MX51_MXC_INT_GPIO3_LOW,
.irq_high = MX51_MXC_INT_GPIO3_HIGH,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2
},
{
.chip.label = "gpio-3",
.base = MX51_IO_ADDRESS(MX51_GPIO4_BASE_ADDR),
.irq = MX51_MXC_INT_GPIO4_LOW,
.irq_high = MX51_MXC_INT_GPIO4_HIGH,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3
},
};

6
arch/arm/plat-mxc/gpio.c
View File

@ -292,6 +292,12 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
/* setup one handler for each entry */
set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
set_irq_data(port[i].irq, &port[i]);
if (port[i].irq_high) {
/* setup handler for GPIO 16 to 31 */
set_irq_chained_handler(port[i].irq_high,
mx3_gpio_irq_handler);
set_irq_data(port[i].irq_high, &port[i]);
}
}
}

1
arch/arm/plat-mxc/include/mach/gpio.h
View File

@ -33,6 +33,7 @@
struct mxc_gpio_port {
void __iomem *base;
int irq;
int irq_high;
int virtual_irq_start;
struct gpio_chip chip;
u32 both_edges;