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SoCFPGA DTS updates for v5.4 

- Add reset properties for various peripherals
 	- QSPI OCP and DMA on Arria10
 	- DMA on Agilex/Stratix10
 - Update NAND controller bindings to match driver update
 - Add NAND controller to Stratix10
 - VINING FPGA board fixups
 	- Update button mapping
 	- Adjust GMAC1 clock and TXD skew settings
 - Add missing reset-names for dma controller
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Merge tag 'socfpga_dts_updates_for_v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt

SoCFPGA DTS updates for v5.4
- Add reset properties for various peripherals
	- QSPI OCP and DMA on Arria10
	- DMA on Agilex/Stratix10
- Update NAND controller bindings to match driver update
- Add NAND controller to Stratix10
- VINING FPGA board fixups
	- Update button mapping
	- Adjust GMAC1 clock and TXD skew settings
- Add missing reset-names for dma controller

* tag 'socfpga_dts_updates_for_v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: dts: socfpga: add missing reset-names for dma
  ARM: dts: socfpga: Adjust GMAC1 clock and TXD lines skew on VINING FPGA
  ARM: dts: socfpga: Fix up button mapping on VINING FPGA
  arm64: dts: stratix10: Add NAND device node
  ARM: dts: socfpga: update to new Denali NAND binding
  arm64: dts: agilex/stratix10: Add reset properties for DMA
  ARM: dts: socfpga: add reset properties for DMA
  ARM: dts: socfpga: add the QSPI OCP reset property on arria10

Link: https://lore.kernel.org/r/20190819141659.26414-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2019-09-03 15:10:33 +02:00
parent 2c70bcf72d d8c1ccac44
commit aa85a28663
6 changed files with 63 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/boot/dts/socfpga.dtsi
View File

@ -85,6 +85,7 @@
clocks = <&l4_main_clk>;
clock-names = "apb_pclk";
resets = <&rst DMA_RESET>;
reset-names = "dma";
};
};
@ -747,7 +748,7 @@
nand0: nand@ff900000 {
#address-cells = <0x1>;
#size-cells = <0x1>;
#size-cells = <0x0>;
compatible = "altr,socfpga-denali-nand";
reg = <0xff900000 0x100000>,
<0xffb80000 0x10000>;

7
arch/arm/boot/dts/socfpga_arria10.dtsi
View File

@ -68,6 +68,8 @@
#dma-requests = <32>;
clocks = <&l4_main_clk>;
clock-names = "apb_pclk";
resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
reset-names = "dma", "dma-ocp";
};
};
@ -660,7 +662,7 @@
nand: nand@ffb90000 {
#address-cells = <1>;
#size-cells = <1>;
#size-cells = <0>;
compatible = "altr,socfpga-denali-nand";
reg = <0xffb90000 0x72000>,
<0xffb80000 0x10000>;
@ -753,7 +755,8 @@
cdns,fifo-width = <4>;
cdns,trigger-address = <0x00000000>;
clocks = <&qspi_clk>;
resets = <&rst QSPI_RESET>;
resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
reset-names = "qspi", "qspi-ocp";
status = "disabled";
};

20
arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts
View File

@ -9,12 +9,18 @@
&nand {
status = "okay";
partition@nand-boot {
label = "Boot and fpga data";
reg = <0x0 0x1C00000>;
};
partition@nand-rootfs {
label = "Root Filesystem - JFFS2";
reg = <0x1C00000 0x6400000>;
nand@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Boot and fpga data";
reg = <0x0 0x1C00000>;
};
partition@1c00000 {
label = "Root Filesystem - JFFS2";
reg = <0x1C00000 0x6400000>;
};
};
};

30
arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
View File

@ -36,21 +36,33 @@
hps_temp0 {
label = "BTN_0"; /* TEMP_OS */
gpios = <&portc 18 GPIO_ACTIVE_LOW>; /* HPS_GPIO60 */
gpios = <&portc 18 GPIO_ACTIVE_LOW>; /* HPS_GPI5 */
linux,code = <BTN_0>;
};
hps_hkey0 {
label = "BTN_1"; /* DIS_PWR */
gpios = <&portc 19 GPIO_ACTIVE_LOW>; /* HPS_GPIO61 */
label = "GP_SWITCH"; /* GP_SWITCH */
gpios = <&portc 19 GPIO_ACTIVE_LOW>; /* HPS_GPI6 */
linux,code = <BTN_1>;
};
hps_hkey1 {
label = "hps_hkey1"; /* POWER_DOWN */
gpios = <&portc 20 GPIO_ACTIVE_LOW>; /* HPS_GPIO62 */
label = "RESET_SWITCH"; /* RESET_SWITCH */
gpios = <&portc 20 GPIO_ACTIVE_LOW>; /* HPS_GPI7 */
linux,code = <BTN_2>;
};
hps_hkey2 {
label = "POWER_DOWN"; /* POWER_DOWN */
gpios = <&portc 4 GPIO_ACTIVE_LOW>; /* HPS_GPIO62 */
linux,code = <KEY_POWER>;
};
hps_hkey3 {
label = "SENSE"; /* SENSE */
gpios = <&porta 9 GPIO_ACTIVE_LOW>; /* HPS_GPIO9 */
linux,code = <BTN_3>;
};
};
regulator-usb-nrst {
@ -84,10 +96,14 @@
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txd0-skew-ps = <0>;
txd1-skew-ps = <0>;
txd2-skew-ps = <0>;
txd3-skew-ps = <0>;
txen-skew-ps = <0>;
txc-skew-ps = <2600>;
txc-skew-ps = <1860>;
rxdv-skew-ps = <0>;
rxc-skew-ps = <2000>;
rxc-skew-ps = <1860>;
};
};
};

18
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
View File

@ -302,6 +302,22 @@
status = "disabled";
};
nand: nand@ffb90000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "altr,socfpga-denali-nand";
reg = <0xffb90000 0x10000>,
<0xffb80000 0x1000>;
reg-names = "nand_data", "denali_reg";
interrupts = <0 97 4>;
clocks = <&clkmgr STRATIX10_NAND_CLK>,
<&clkmgr STRATIX10_NAND_X_CLK>,
<&clkmgr STRATIX10_NAND_ECC_CLK>;
clock-names = "nand", "nand_x", "ecc";
resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
status = "disabled";
};
ocram: sram@ffe00000 {
compatible = "mmio-sram";
reg = <0xffe00000 0x100000>;
@ -324,6 +340,8 @@
#dma-requests = <32>;
clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
clock-names = "apb_pclk";
resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
reset-names = "dma", "dma-ocp";
};
rst: rstmgr@ffd11000 {

2
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
View File

@ -249,6 +249,8 @@
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
reset-names = "dma", "dma-ocp";
};
rst: rstmgr@ffd11000 {