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mtd: spi-nor: Move Intel bits out of core.c 

Create a SPI NOR manufacturer driver for Intel chips, and move the
Intel definitions outside of core.c.

Signed-off-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
This commit is contained in:
Boris Brezillon 2020-03-13 19:42:43 +00:00 committed by Tudor Ambarus
parent acb96ecd59
commit aa6351877f
No known key found for this signature in database
GPG Key ID: 4B554F47A58D14E9
4 changed files with 35 additions and 14 deletions
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1
drivers/mtd/spi-nor/Makefile
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@ -7,4 +7,5 @@ spi-nor-objs += esmt.o
spi-nor-objs += everspin.o
spi-nor-objs += fujitsu.o
spi-nor-objs += gigadevice.o
spi-nor-objs += intel.o
obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o

15
drivers/mtd/spi-nor/core.c
View File

@ -2066,11 +2066,6 @@ static struct spi_nor_fixups mx25l25635_fixups = {
* old entries may be missing 4K flag.
*/
static const struct flash_info spi_nor_ids[] = {
/* Intel/Numonyx -- xxxs33b */
{ "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
{ "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
{ "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
/* ISSI */
{ "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
{ "is25lq040b", INFO(0x9d4013, 0, 64 * 1024, 8,
@ -2372,6 +2367,7 @@ static const struct spi_nor_manufacturer *manufacturers[] = {
&spi_nor_everspin,
&spi_nor_fujitsu,
&spi_nor_gigadevice,
&spi_nor_intel,
};
static const struct flash_info *
@ -3151,11 +3147,6 @@ static int spi_nor_setup(struct spi_nor *nor,
return nor->params.setup(nor, hwcaps);
}
static void intel_set_default_init(struct spi_nor *nor)
{
nor->flags |= SNOR_F_HAS_LOCK;
}
static void issi_set_default_init(struct spi_nor *nor)
{
nor->params.quad_enable = spi_nor_sr1_bit6_quad_enable;
@ -3194,10 +3185,6 @@ static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
{
/* Init flash parameters based on MFR */
switch (JEDEC_MFR(nor->info)) {
case SNOR_MFR_INTEL:
intel_set_default_init(nor);
break;
case SNOR_MFR_ISSI:
issi_set_default_init(nor);
break;

1
drivers/mtd/spi-nor/core.h
View File

@ -173,6 +173,7 @@ extern const struct spi_nor_manufacturer spi_nor_esmt;
extern const struct spi_nor_manufacturer spi_nor_everspin;
extern const struct spi_nor_manufacturer spi_nor_fujitsu;
extern const struct spi_nor_manufacturer spi_nor_gigadevice;
extern const struct spi_nor_manufacturer spi_nor_intel;
int spi_nor_write_enable(struct spi_nor *nor);
int spi_nor_write_disable(struct spi_nor *nor);

32
drivers/mtd/spi-nor/intel.c Normal file
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@ -0,0 +1,32 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2005, Intec Automation Inc.
* Copyright (C) 2014, Freescale Semiconductor, Inc.
*/
#include <linux/mtd/spi-nor.h>
#include "core.h"
static const struct flash_info intel_parts[] = {
/* Intel/Numonyx -- xxxs33b */
{ "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
{ "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
{ "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
};
static void intel_default_init(struct spi_nor *nor)
{
nor->flags |= SNOR_F_HAS_LOCK;
}
static const struct spi_nor_fixups intel_fixups = {
.default_init = intel_default_init,
};
const struct spi_nor_manufacturer spi_nor_intel = {
.name = "intel",
.parts = intel_parts,
.nparts = ARRAY_SIZE(intel_parts),
.fixups = &intel_fixups,
};