treewide: fix "distingush" typo
Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
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@ -45,7 +45,7 @@ static inline void get_new_mmu_context(struct mm_struct *mm)
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Flush all TLB and start new cycle. */
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local_flush_tlb_all();
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/* Fix version if needed.
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Note that we avoid version #0 to distingush NO_CONTEXT. */
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Note that we avoid version #0 to distinguish NO_CONTEXT. */
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if (!mc)
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mmu_context_cache = mc = MMU_CONTEXT_FIRST_VERSION;
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}
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@ -71,7 +71,7 @@ static inline unsigned long allocate_mmu_context(struct mm_struct *mm)
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local_flush_tlb_all();
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/* fix the TLB version if needed (we avoid version #0 so as to
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* distingush MMU_NO_CONTEXT) */
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* distinguish MMU_NO_CONTEXT) */
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if (!mc)
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*pmc = mc = MMU_CONTEXT_FIRST_VERSION;
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}
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@ -31,7 +31,7 @@
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#define NVRW_CNT 0x20
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/*
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* Set oops header version to distingush between old and new format header.
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* Set oops header version to distinguish between old and new format header.
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* lnx,oops-log partition max size is 4000, header version > 4000 will
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* help in identifying new header.
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*/
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@ -81,7 +81,7 @@ static inline void get_mmu_context(struct mm_struct *mm, unsigned int cpu)
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/*
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* Fix version; Note that we avoid version #0
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* to distingush NO_CONTEXT.
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* to distinguish NO_CONTEXT.
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*/
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if (!asid)
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asid = MMU_CONTEXT_FIRST_VERSION;
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@ -339,7 +339,7 @@ static void amd_get_topology(struct cpuinfo_x86 *c)
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#endif
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/*
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* On a AMD dual core setup the lower bits of the APIC id distingush the cores.
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* On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
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* Assumes number of cores is a power of two.
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*/
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static void amd_detect_cmp(struct cpuinfo_x86 *c)
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@ -1031,7 +1031,7 @@ static void i8042_controller_reset(bool force_reset)
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/*
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* i8042_panic_blink() will turn the keyboard LEDs on or off and is called
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* when kernel panics. Flashing LEDs is useful for users running X who may
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* not see the console and will help distingushing panics from "real"
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* not see the console and will help distinguishing panics from "real"
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* lockups.
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*
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* Note that DELAY has a limit of 10ms so we will not get stuck here
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@ -49,7 +49,7 @@
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* can't distinguish between a clean block that has been generated
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* from parity calculations, and a clean block that has been
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* successfully written to the spare ( or to parity when resyncing).
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* To distingush these states we have a stripe bit STRIPE_INSYNC that
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* To distinguish these states we have a stripe bit STRIPE_INSYNC that
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* is set whenever a write is scheduled to the spare, or to the parity
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* disc if there is no spare. A sync request clears this bit, and
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* when we find it set with no buffers locked, we know the sync is
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