TI K3 device tree updates for v6.1
New Features: AM62A: * Basic support for AM62A SoC and SK Board AM62: * EPWM support AM64: * GPMC, LED, Crypto accelerator support Fixes: J7200 pinmux node update Fixes for Crypto and RNG accelerators on AM65, J721e, J7200 Cleanups: Reorder SoC compatible and pinmux macros alphabetically -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEEyRC2zAhGcGjrhiNExEYeRXyRFuMFAmMq5n4QHHZpZ25lc2hy QHRpLmNvbQAKCRDERh5FfJEW44z/CACMrwIDvNby4wK1TGpv2jtjW2UD/6Bo23ZL HYRy2kkNBa5hMbhGZGh5+GznOXyoZJD07OmuYLq8wdxIvo19QHOjAK7YLuHGvpel u8o1IPXQEDylgbpcm06vCF/C73UGb8ozBcPP56v8wYhq/AeD7iAd9VtkxzBwdmpu hG/X5r1q0LJbxDLrNaI8jjsOjrc2ep5LIbnqzibKZR1+JX1E2LSezDVxjOEtG3aC Sl9kgA8mr96nB2WTcAV1oDuaiI9mlH6HEBaofTdFRU4gA9hu9Z7lWBBF3G+GKnTE bJIgSxQpzAr1TxqKqIRMzWa9/Xrg6O+M9MBs6RMb0oDMvmb4+wTg =fi01 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmMtw0EACgkQmmx57+YA GNnDCw/8DcqGvp/NJjhmYgfmBL94OHCL6NseST0QRdqBxhQbfskc2rfMf+lxbNR8 o/Ic5YRwo5z54z34dpw3bi+N0dUYE6V80RJBPOSTlX/Dk3thb1/MyxZqTALhduRU BPu/fwZFE34uOi6xy6e8cfZqXtnDX6dHvtw+XCPPJ8Tb34SAmAvkQ/LCLrfS6wjw xIGIIVwCiIAHK4FLSd5rvnyeVA0CfKEeDJ405Wob7cKz/aUAwUiwbRPszP9+62JC XHvvxZoeFgoG4UhN57RN7E4tkmBkKNYMzNGLd6bKD45YJk4MwzyW560nMcrJ25IJ 3GimiaFXKG8NRX2Ai0cWyuAp4vOFkygQ2xpMVMjfr0gBkSbV8vuGNUK5yXhkT2V3 JBz5CA3lo3Di3zTk8qXRRXBDeYIcTPxSYiCpnhuMhdCn282y0VL3h1padgR7W8eg F9ikkrkh6T5IAq5yzXHO+FRBaZRmecrHbbsS2H7vnzGLWHCG5ynle/5BeOTVXOeF 2X7IcPFgzBGFLe02THIooFkeBQ3X0fIn/uJ4VxqwUshuc8BLv5ys6JLFMoHY99Z/ PI4SJ5tdAo3pacsW5RfvMHZ3jFJwRo2i/kmy95vyeEGm0By1js8eziKi1ehsD195 tNQSd+giXRBtDGAr/KrRWfwH+MxNNj+g6aWt80HSk2uG3Pr8Qek= =XhYf -----END PGP SIGNATURE----- Merge tag 'ti-k3-dt-for-v6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into arm/dt TI K3 device tree updates for v6.1 New Features: AM62A: * Basic support for AM62A SoC and SK Board AM62: * EPWM support AM64: * GPMC, LED, Crypto accelerator support Fixes: J7200 pinmux node update Fixes for Crypto and RNG accelerators on AM65, J721e, J7200 Cleanups: Reorder SoC compatible and pinmux macros alphabetically * tag 'ti-k3-dt-for-v6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: (22 commits) arm64: dts: ti: k3-j7200: fix main pinmux range arm64: dts: ti: Add support for AM62A7-SK arm64: dts: ti: Introduce AM62A7 family of SoCs dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM62A dt-bindings: arm: ti: Add bindings for AM62A7 SoC dt-bindings: arm: ti: Rearrange IOPAD macros alphabetically arm64: dts: ti: k3-am625-sk: Add epwm nodes arm64: dts: ti: k3-am62-main: Add epwm nodes arm64: dts: ti: k3-am642-sk: Add DT entry for onboard LEDs arm64: dts: ti: k3-j7200-mcu-wakeup: Add SA2UL node arm64: dts: ti: k3-am65-main: Do not exclusively claim SA2UL arm64: dts: ti: k3-am65-main: Move SA2UL to unused PSI-L thread ID arm64: dts: ti: k3-am65-main: Disable RNG node arm64: dts: ti: k3-j7200-main: Add main domain watchdog entries arm64: dts: ti: k3-am64-main: Add ELM (Error Location Module) node arm64: dts: ti: k3-am64-main: Add GPMC memory controller node arm64: dts: ti: k3-j721e-main: fix RNG node clock id arm64: dts: ti: k3-am64-main: Enable crypto accelerator arm64: dts: ti: k3-am64: Add SA2UL address space to Main CBASS ranges arm64: dts: ti: k3-am64-main: Add main_cpts label ... Link: https://lore.kernel.org/r/44729b46-27f9-94a0-17ed-8868649a4a0a@ti.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
aa577af3de
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@ -19,32 +19,11 @@ properties:
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compatible:
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oneOf:
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- description: K3 AM654 SoC
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- description: K3 AM62A7 SoC
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items:
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- enum:
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- ti,am654-evm
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- siemens,iot2050-basic
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- siemens,iot2050-basic-pg2
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- siemens,iot2050-advanced
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- siemens,iot2050-advanced-pg2
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- const: ti,am654
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- description: K3 J721E SoC
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oneOf:
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- const: ti,j721e
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- items:
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- enum:
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- ti,j721e-evm
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- ti,j721e-sk
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- const: ti,j721e
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- description: K3 J7200 SoC
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oneOf:
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- const: ti,j7200
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- items:
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- enum:
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- ti,j7200-evm
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- const: ti,j7200
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- ti,am62a7-sk
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- const: ti,am62a7
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- description: K3 AM625 SoC
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items:
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@ -59,6 +38,33 @@ properties:
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- ti,am642-sk
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- const: ti,am642
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- description: K3 AM654 SoC
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items:
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- enum:
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- siemens,iot2050-advanced
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- siemens,iot2050-advanced-pg2
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- siemens,iot2050-basic
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- siemens,iot2050-basic-pg2
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- ti,am654-evm
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- const: ti,am654
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- description: K3 J7200 SoC
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oneOf:
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- const: ti,j7200
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- items:
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- enum:
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- ti,j7200-evm
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- const: ti,j7200
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- description: K3 J721E SoC
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oneOf:
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- const: ti,j721e
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- items:
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- enum:
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- ti,j721e-evm
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- ti,j721e-sk
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- const: ti,j721e
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- description: K3 J721s2 SoC
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items:
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- enum:
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@ -23,3 +23,5 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
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@ -54,6 +54,12 @@
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reg = <0x4044 0x8>;
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#phy-cells = <1>;
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};
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epwm_tbclk: clock@4130 {
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compatible = "ti,am62-epwm-tbclk", "syscon";
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reg = <0x4130 0x4>;
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#clock-cells = <1>;
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};
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};
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dmss: bus@48000000 {
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@ -584,4 +590,31 @@
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interrupt-names = "int0", "int1";
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bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
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};
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epwm0: pwm@23000000 {
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compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x00 0x23000000 0x00 0x100>;
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power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
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clock-names = "tbclk", "fck";
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};
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epwm1: pwm@23010000 {
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compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x00 0x23010000 0x00 0x100>;
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power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
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clock-names = "tbclk", "fck";
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};
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epwm2: pwm@23020000 {
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compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x00 0x23020000 0x00 0x100>;
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power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
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clock-names = "tbclk", "fck";
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};
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};
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@ -502,3 +502,15 @@
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&main_mcan0 {
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status = "disabled";
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};
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&epwm0 {
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status = "disabled";
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};
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&epwm1 {
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status = "disabled";
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};
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&epwm2 {
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status = "disabled";
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};
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@ -0,0 +1,298 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for AM62A SoC Family Main Domain peripherals
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*
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* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_main {
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oc_sram: sram@70000000 {
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compatible = "mmio-sram";
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reg = <0x00 0x70000000 0x00 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x00 0x70000000 0x10000>;
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};
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gic500: interrupt-controller@1800000 {
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compatible = "arm,gic-v3";
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reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
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<0x00 0x01880000 0x00 0xc0000>, /* GICR */
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<0x00 0x01880000 0x00 0xc0000>, /* GICR */
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<0x01 0x00000000 0x00 0x2000>, /* GICC */
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<0x01 0x00010000 0x00 0x1000>, /* GICH */
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<0x01 0x00020000 0x00 0x2000>; /* GICV */
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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#interrupt-cells = <3>;
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interrupt-controller;
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/*
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* vcpumntirq:
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* virtual CPU interface maintenance interrupt
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*/
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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gic_its: msi-controller@1820000 {
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compatible = "arm,gic-v3-its";
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reg = <0x00 0x01820000 0x00 0x10000>;
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socionext,synquacer-pre-its = <0x1000000 0x400000>;
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msi-controller;
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#msi-cells = <1>;
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};
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};
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main_conf: syscon@100000 {
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compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
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reg = <0x00 0x00100000 0x00 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00 0x00 0x00100000 0x20000>;
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};
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dmss: bus@48000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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dma-ranges;
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ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>;
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ti,sci-dev-id = <25>;
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secure_proxy_main: mailbox@4d000000 {
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compatible = "ti,am654-secure-proxy";
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reg = <0x00 0x4d000000 0x00 0x80000>,
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<0x00 0x4a600000 0x00 0x80000>,
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<0x00 0x4a400000 0x00 0x80000>;
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reg-names = "target_data", "rt", "scfg";
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#mbox-cells = <1>;
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interrupt-names = "rx_012";
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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dmsc: system-controller@44043000 {
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compatible = "ti,k2g-sci";
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reg = <0x00 0x44043000 0x00 0xfe0>;
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reg-names = "debug_messages";
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ti,host-id = <12>;
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mbox-names = "rx", "tx";
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mboxes= <&secure_proxy_main 12>,
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<&secure_proxy_main 13>;
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k3_pds: power-controller {
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compatible = "ti,sci-pm-domain";
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#power-domain-cells = <2>;
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};
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k3_clks: clock-controller {
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compatible = "ti,k2g-sci-clk";
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#clock-cells = <2>;
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};
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k3_reset: reset-controller {
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compatible = "ti,sci-reset";
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#reset-cells = <2>;
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};
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};
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main_pmx0: pinctrl@f4000 {
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compatible = "pinctrl-single";
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reg = <0x00 0xf4000 0x00 0x2ac>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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main_uart0: serial@2800000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02800000 0x00 0x100>;
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interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 146 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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main_uart1: serial@2810000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02810000 0x00 0x100>;
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interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 152 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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main_uart2: serial@2820000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02820000 0x00 0x100>;
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interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 153 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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main_uart3: serial@2830000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02830000 0x00 0x100>;
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interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 154 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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main_uart4: serial@2840000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02840000 0x00 0x100>;
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interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 155 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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main_uart5: serial@2850000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02850000 0x00 0x100>;
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interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 156 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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main_uart6: serial@2860000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02860000 0x00 0x100>;
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interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 158 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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main_i2c0: i2c@20000000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x00 0x20000000 0x00 0x100>;
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interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 102 2>;
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clock-names = "fck";
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status = "disabled";
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};
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main_i2c1: i2c@20010000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x00 0x20010000 0x00 0x100>;
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interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 103 2>;
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clock-names = "fck";
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status = "disabled";
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};
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main_i2c2: i2c@20020000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x00 0x20020000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
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#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 104 2>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_i2c3: i2c@20030000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x20030000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 105 2>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_gpio_intr: interrupt-controller@a00000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x00 0x00a00000 0x00 0x800>;
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <1>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <3>;
|
||||
ti,interrupt-ranges = <0 32 16>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_gpio0: gpio@600000 {
|
||||
compatible = "ti,am64-gpio", "ti,keystone-gpio";
|
||||
reg = <0x00 0x00600000 0x0 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&main_gpio_intr>;
|
||||
interrupts = <190>, <191>, <192>,
|
||||
<193>, <194>, <195>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <87>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 77 0>;
|
||||
clock-names = "gpio";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_gpio1: gpio@601000 {
|
||||
compatible = "ti,am64-gpio", "ti,keystone-gpio";
|
||||
reg = <0x00 0x00601000 0x0 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&main_gpio_intr>;
|
||||
interrupts = <180>, <181>, <182>,
|
||||
<183>, <184>, <185>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <88>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 78 0>;
|
||||
clock-names = "gpio";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci1: mmc@fa00000 {
|
||||
compatible = "ti,am62-sdhci";
|
||||
reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
|
||||
clock-names = "clk_ahb", "clk_xin";
|
||||
ti,trm-icp = <0x2>;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
ti,otap-del-sel-sd-hs = <0x0>;
|
||||
ti,otap-del-sel-sdr12 = <0xf>;
|
||||
ti,otap-del-sel-sdr25 = <0xf>;
|
||||
ti,otap-del-sel-sdr50 = <0xc>;
|
||||
ti,otap-del-sel-sdr104 = <0x6>;
|
||||
ti,otap-del-sel-ddr50 = <0x9>;
|
||||
ti,itap-del-sel-legacy = <0x0>;
|
||||
ti,itap-del-sel-sd-hs = <0x0>;
|
||||
ti,itap-del-sel-sdr12 = <0x0>;
|
||||
ti,itap-del-sel-sdr25 = <0x0>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
bus-width = <4>;
|
||||
no-1-8-v;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM625 SoC Family MCU Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&cbass_mcu {
|
||||
mcu_pmx0: pinctrl@4084000 {
|
||||
compatible = "pinctrl-single";
|
||||
reg = <0x00 0x04084000 0x00 0x88>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_uart0: serial@4a00000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x04a00000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 149 0>;
|
||||
clock-names = "fclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_i2c0: i2c@4900000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x04900000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 106 2>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM62A SoC Family Wakeup Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&cbass_wakeup {
|
||||
wkup_conf: syscon@43000000 {
|
||||
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
|
||||
reg = <0x00 0x43000000 0x00 0x20000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00 0x00 0x43000000 0x20000>;
|
||||
|
||||
chipid: chipid@14 {
|
||||
compatible = "ti,am654-chipid";
|
||||
reg = <0x14 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
wkup_uart0: serial@2b300000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x2b300000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 114 0>;
|
||||
clock-names = "fclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wkup_i2c0: i2c@2b200000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x02b200000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 107 4>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wkup_rtc0: rtc@2b1f0000 {
|
||||
compatible = "ti,am62-rtc";
|
||||
reg = <0x00 0x2b1f0000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&k3_clks 117 6> , <&k3_clks 117 0>;
|
||||
clock-names = "vbus", "osc32k";
|
||||
power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
|
||||
wakeup-source;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,122 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM62A SoC Family
|
||||
*
|
||||
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/k3.h>
|
||||
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||
|
||||
/ {
|
||||
model = "Texas Instruments K3 AM62A SoC";
|
||||
compatible = "ti,am62a7";
|
||||
interrupt-parent = <&gic500>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
chosen { };
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
psci: psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
a53_timer0: timer-cl0-cpu0 {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
cbass_main: bus@f0000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
|
||||
<0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
|
||||
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
|
||||
<0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
|
||||
<0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
|
||||
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
|
||||
<0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
|
||||
<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
|
||||
<0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
|
||||
<0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
|
||||
<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
|
||||
<0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
|
||||
<0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
|
||||
<0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
|
||||
<0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
|
||||
<0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
|
||||
<0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
|
||||
<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
|
||||
<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
|
||||
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
|
||||
<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
|
||||
<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
|
||||
<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
|
||||
<0x00 0x7e000000 0x00 0x7e000000 0x00 0x00100000>, /* C7x_0 */
|
||||
<0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
|
||||
|
||||
/* MCU Domain Range */
|
||||
<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
|
||||
<0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
|
||||
<0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
|
||||
<0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU R5 IRAM0 */
|
||||
<0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, /* MCU R5 IRAM1 */
|
||||
|
||||
/* Wakeup Domain Range */
|
||||
<0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>,
|
||||
<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
|
||||
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>,
|
||||
<0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM */
|
||||
<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM */
|
||||
|
||||
cbass_mcu: bus@4000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */
|
||||
<0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
|
||||
<0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
|
||||
<0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */
|
||||
<0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */
|
||||
};
|
||||
|
||||
cbass_wakeup: bus@b00000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
|
||||
<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
|
||||
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */
|
||||
<0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
|
||||
<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Now include the peripherals for each bus segments */
|
||||
#include "k3-am62a-main.dtsi"
|
||||
#include "k3-am62a-mcu.dtsi"
|
||||
#include "k3-am62a-wakeup.dtsi"
|
||||
|
|
@ -0,0 +1,223 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* AM62A SK: https://www.ti.com/lit/zip/sprr459
|
||||
*
|
||||
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "k3-am62a7.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am62a7-sk", "ti,am62a7";
|
||||
model = "Texas Instruments AM62A7 SK";
|
||||
|
||||
aliases {
|
||||
serial2 = &main_uart0;
|
||||
mmc1 = &sdhci1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 2G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secure_tfa_ddr: tfa@9e780000 {
|
||||
reg = <0x00 0x9e780000 0x00 0x80000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9c900000 0x00 0x01e00000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
vmain_pd: regulator-0 {
|
||||
/* TPS25750 PD CONTROLLER OUTPUT */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmain_pd";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_5v0: regulator-1 {
|
||||
/* Output of TPS63070 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vmain_pd>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_3v3_sys: regulator-2 {
|
||||
/* output of LM5141-Q1 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_3v3_sys";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vmain_pd>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_mmc1: regulator-3 {
|
||||
/* TPS22918DBVR */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_mmc1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usr_led_pins_default>;
|
||||
|
||||
led-0 {
|
||||
label = "am62a-sk:green:heartbeat";
|
||||
gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_uart0_pins_default: main-uart0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
|
||||
AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c0_pins_default: main-i2c0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
|
||||
AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c1_pins_default: main-i2c1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62AX_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
|
||||
AM62AX_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c2_pins_default: main-i2c2-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62AX_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
|
||||
AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mmc1_pins_default: main-mmc1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
|
||||
AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
|
||||
AM62AX_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
|
||||
AM62AX_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
|
||||
AM62AX_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
|
||||
AM62AX_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
|
||||
AM62AX_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
|
||||
>;
|
||||
};
|
||||
|
||||
usr_led_pins_default: usr-led-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62AX_IOPAD(0x244, PIN_OUTPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&main_i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c1_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
exp1: gpio@22 {
|
||||
compatible = "ti,tca6424";
|
||||
reg = <0x22>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
|
||||
"BT_EN_SOC", "MMC1_SD_EN",
|
||||
"VPP_EN", "EXP_PS_3V3_En",
|
||||
"EXP_PS_5V0_En", "EXP_HAT_DETECT",
|
||||
"GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
|
||||
"UART1_FET_BUF_EN", "BT_UART_WAKE_SOC",
|
||||
"GPIO_HDMI_RSTn", "CSI_GPIO0",
|
||||
"CSI_GPIO1", "WLAN_ALERTn",
|
||||
"HDMI_INTn", "TEST_GPIO2",
|
||||
"MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
|
||||
"MCASP1_FET_SEL", "UART1_FET_SEL",
|
||||
"PD_I2C_IRQ", "IO_EXP_TEST_LED";
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
/* SD/MMC */
|
||||
status = "okay";
|
||||
vmmc-supply = <&vdd_mmc1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&main_gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_gpio_intr {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
};
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM62A7 SoC family in Quad core configuration
|
||||
*
|
||||
* TRM: https://www.ti.com/lit/zip/spruj16
|
||||
*
|
||||
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am62a.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0: cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&cpu2>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&cpu3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x000>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x001>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x002>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x003>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-size = <0x40000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
};
|
||||
};
|
||||
|
|
@ -550,7 +550,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
cpts@39000000 {
|
||||
main_cpts0: cpts@39000000 {
|
||||
compatible = "ti,j721e-cpts";
|
||||
reg = <0x0 0x39000000 0x0 0x400>;
|
||||
reg-names = "cpts";
|
||||
|
|
@ -1308,4 +1308,52 @@
|
|||
interrupt-names = "int0", "int1";
|
||||
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
|
||||
};
|
||||
|
||||
crypto: crypto@40900000 {
|
||||
compatible = "ti,am64-sa2ul";
|
||||
reg = <0x00 0x40900000 0x00 0x1200>;
|
||||
power-domains = <&k3_pds 133 TI_SCI_PD_SHARED>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
|
||||
dmas = <&main_pktdma 0xc001 0>, <&main_pktdma 0x4002 0>,
|
||||
<&main_pktdma 0x4003 0>;
|
||||
dma-names = "tx", "rx1", "rx2";
|
||||
|
||||
rng: rng@40910000 {
|
||||
compatible = "inside-secure,safexcel-eip76";
|
||||
reg = <0x00 0x40910000 0x00 0x7d>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&k3_clks 133 1>;
|
||||
status = "disabled"; /* Used by OP-TEE */
|
||||
};
|
||||
};
|
||||
|
||||
gpmc0: memory-controller@3b000000 {
|
||||
compatible = "ti,am64-gpmc";
|
||||
power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 80 0>;
|
||||
clock-names = "fck";
|
||||
reg = <0x00 0x03b000000 0x00 0x400>,
|
||||
<0x00 0x050000000 0x00 0x8000000>;
|
||||
reg-names = "cfg", "data";
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpmc,num-cs = <3>;
|
||||
gpmc,num-waitpins = <2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
elm0: ecc@25010000 {
|
||||
compatible = "ti,am64-elm";
|
||||
reg = <0x00 0x25010000 0x00 0x2000>;
|
||||
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 54 0>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -82,6 +82,7 @@
|
|||
<0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
|
||||
<0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */
|
||||
<0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */
|
||||
<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA2_UL0 */
|
||||
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */
|
||||
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
|
||||
<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */
|
||||
|
|
|
|||
|
|
@ -676,3 +676,11 @@
|
|||
pinctrl-0 = <&main_mcan1_pins_default>;
|
||||
phys = <&transceiver2>;
|
||||
};
|
||||
|
||||
&gpmc0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&elm0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include "k3-am642.dtsi"
|
||||
|
||||
/ {
|
||||
|
|
@ -150,6 +151,74 @@
|
|||
vin-supply = <&com8_ls_en>;
|
||||
gpio = <&main_gpio0 48 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led-controller {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led-0 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
function-enumerator = <1>;
|
||||
gpios = <&exp2 0 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-1 {
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
function-enumerator = <2>;
|
||||
gpios = <&exp2 1 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-2 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
function-enumerator = <3>;
|
||||
gpios = <&exp2 2 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-3 {
|
||||
color = <LED_COLOR_ID_AMBER>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
function-enumerator = <4>;
|
||||
gpios = <&exp2 3 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-4 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
function-enumerator = <5>;
|
||||
gpios = <&exp2 4 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-5 {
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
function-enumerator = <6>;
|
||||
gpios = <&exp2 5 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-6 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
function-enumerator = <7>;
|
||||
gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-7 {
|
||||
color = <LED_COLOR_ID_AMBER>;
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
function-enumerator = <8>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
gpios = <&exp2 7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
|
|
@ -330,6 +399,14 @@
|
|||
"VPP_LDO_EN", "RPI_PS_3V3_En",
|
||||
"RPI_PS_5V0_En", "RPI_HAT_DETECT";
|
||||
};
|
||||
|
||||
exp2: gpio@60 {
|
||||
compatible = "ti,tpic2810";
|
||||
reg = <0x60>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "LED1","LED2","LED3","LED4","LED5","LED6","LED7","LED8";
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c3 {
|
||||
|
|
@ -607,3 +684,11 @@
|
|||
&main_mcan1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&gpmc0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&elm0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -112,13 +112,13 @@
|
|||
crypto: crypto@4e00000 {
|
||||
compatible = "ti,am654-sa2ul";
|
||||
reg = <0x0 0x4e00000 0x0 0x1200>;
|
||||
power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>;
|
||||
power-domains = <&k3_pds 136 TI_SCI_PD_SHARED>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
|
||||
|
||||
dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
|
||||
<&main_udmap 0x4001>;
|
||||
dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>,
|
||||
<&main_udmap 0x4003>;
|
||||
dma-names = "tx", "rx1", "rx2";
|
||||
dma-coherent;
|
||||
|
||||
|
|
@ -127,6 +127,7 @@
|
|||
reg = <0x0 0x4e10000 0x0 0x7d>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&k3_clks 136 1>;
|
||||
status = "disabled"; /* Used by OP-TEE */
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -134,12 +134,6 @@
|
|||
>;
|
||||
};
|
||||
|
||||
main_usbss0_pins_default: main-usbss0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
|
||||
|
|
@ -147,6 +141,14 @@
|
|||
};
|
||||
};
|
||||
|
||||
&main_pmx1 {
|
||||
main_usbss0_pins_default: main-usbss0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_uart0 {
|
||||
/* Wakeup UART is used by System firmware */
|
||||
status = "reserved";
|
||||
|
|
|
|||
|
|
@ -295,7 +295,16 @@
|
|||
main_pmx0: pinctrl@11c000 {
|
||||
compatible = "pinctrl-single";
|
||||
/* Proxy 0 addressing */
|
||||
reg = <0x00 0x11c000 0x00 0x2b4>;
|
||||
reg = <0x00 0x11c000 0x00 0x10c>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
main_pmx1: pinctrl@11c11c {
|
||||
compatible = "pinctrl-single";
|
||||
/* Proxy 0 addressing */
|
||||
reg = <0x00 0x11c11c 0x00 0xc>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
|
|
@ -739,6 +748,24 @@
|
|||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
watchdog0: watchdog@2200000 {
|
||||
compatible = "ti,j7-rti-wdt";
|
||||
reg = <0x0 0x2200000 0x0 0x100>;
|
||||
clocks = <&k3_clks 252 1>;
|
||||
power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
|
||||
assigned-clocks = <&k3_clks 252 1>;
|
||||
assigned-clock-parents = <&k3_clks 252 5>;
|
||||
};
|
||||
|
||||
watchdog1: watchdog@2210000 {
|
||||
compatible = "ti,j7-rti-wdt";
|
||||
reg = <0x0 0x2210000 0x0 0x100>;
|
||||
clocks = <&k3_clks 253 1>;
|
||||
power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
|
||||
assigned-clocks = <&k3_clks 253 1>;
|
||||
assigned-clock-parents = <&k3_clks 253 5>;
|
||||
};
|
||||
|
||||
main_r5fss0: r5fss@5c00000 {
|
||||
compatible = "ti,j7200-r5fss";
|
||||
ti,cluster-mode = <1>;
|
||||
|
|
|
|||
|
|
@ -375,4 +375,24 @@
|
|||
ti,loczrama = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
mcu_crypto: crypto@40900000 {
|
||||
compatible = "ti,j721e-sa2ul";
|
||||
reg = <0x00 0x40900000 0x00 0x1200>;
|
||||
power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
|
||||
dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
|
||||
<&mcu_udmap 0x7503>;
|
||||
dma-names = "tx", "rx1", "rx2";
|
||||
dma-coherent;
|
||||
|
||||
rng: rng@40910000 {
|
||||
compatible = "inside-secure,safexcel-eip76";
|
||||
reg = <0x00 0x40910000 0x00 0x7d>;
|
||||
interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled"; /* Used by OP-TEE */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -343,7 +343,7 @@
|
|||
compatible = "inside-secure,safexcel-eip76";
|
||||
reg = <0x0 0x4e10000 0x0 0x7d>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&k3_clks 264 1>;
|
||||
clocks = <&k3_clks 264 2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -29,19 +29,22 @@
|
|||
#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP)
|
||||
#define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN)
|
||||
|
||||
#define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue