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drm/amdgpu: refine uvd_4.2 clock gate sequence. 

1. partial revert commit 91db308d6e96.
   not set uvd bypass mode.
2. enable uvd cg before initialize uvd.
3. set uvd clock to default value 100MHz.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2016-11-04 20:35:46 +08:00 committed by Alex Deucher
parent dc2f8a9aa9
commit aa4747c00a
2 changed files with 9 additions and 39 deletions
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8
drivers/gpu/drm/amd/amdgpu/ci_dpm.c
View File

@ -4202,11 +4202,6 @@ static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
if (!gate) { if (!gate) {
/* turn the clocks on when decoding */ /* turn the clocks on when decoding */
ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
AMD_CG_STATE_UNGATE);
if (ret)
return ret;
if (pi->caps_uvd_dpm || if (pi->caps_uvd_dpm ||
(adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
pi->smc_state_table.UvdBootLevel = 0; pi->smc_state_table.UvdBootLevel = 0;
@ -4223,9 +4218,6 @@ static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
ret = ci_enable_uvd_dpm(adev, false); ret = ci_enable_uvd_dpm(adev, false);
if (ret) if (ret)
return ret; return ret;
ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
AMD_CG_STATE_GATE);
} }
return ret; return ret;

40
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
View File

@ -45,7 +45,8 @@ static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev);
static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev); static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev);
static int uvd_v4_2_start(struct amdgpu_device *adev); static int uvd_v4_2_start(struct amdgpu_device *adev);
static void uvd_v4_2_stop(struct amdgpu_device *adev); static void uvd_v4_2_stop(struct amdgpu_device *adev);
static int uvd_v4_2_set_clockgating_state(void *handle,
enum amd_clockgating_state state);
/** /**
* uvd_v4_2_ring_get_rptr - get read pointer * uvd_v4_2_ring_get_rptr - get read pointer
* *
@ -154,9 +155,9 @@ static int uvd_v4_2_hw_init(void *handle)
uint32_t tmp; uint32_t tmp;
int r; int r;
/* raise clocks while booting up the VCPU */ uvd_v4_2_init_cg(adev);
amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); uvd_v4_2_set_clockgating_state(adev, AMD_CG_STATE_GATE);
amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
r = uvd_v4_2_start(adev); r = uvd_v4_2_start(adev);
if (r) if (r)
goto done; goto done;
@ -196,8 +197,6 @@ static int uvd_v4_2_hw_init(void *handle)
amdgpu_ring_commit(ring); amdgpu_ring_commit(ring);
done: done:
/* lower clocks again */
amdgpu_asic_set_uvd_clocks(adev, 0, 0);
if (!r) if (!r)
DRM_INFO("UVD initialized successfully.\n"); DRM_INFO("UVD initialized successfully.\n");
@ -274,9 +273,6 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)
uvd_v4_2_mc_resume(adev); uvd_v4_2_mc_resume(adev);
/* disable clock gating */
WREG32(mmUVD_CGC_GATE, 0);
/* disable interupt */ /* disable interupt */
WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
@ -568,8 +564,6 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)
WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
uvd_v4_2_init_cg(adev);
} }
static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,
@ -579,7 +573,7 @@ static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
data = 0xfff; data |= 0xfff;
WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
orig = data = RREG32(mmUVD_CGC_CTRL); orig = data = RREG32(mmUVD_CGC_CTRL);
@ -686,34 +680,18 @@ static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev,
return 0; return 0;
} }
static void uvd_v5_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
{
u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
if (enable)
tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
else
tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
}
static int uvd_v4_2_set_clockgating_state(void *handle, static int uvd_v4_2_set_clockgating_state(void *handle,
enum amd_clockgating_state state) enum amd_clockgating_state state)
{ {
bool gate = false; bool gate = false;
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (state == AMD_CG_STATE_GATE)
gate = true;
uvd_v5_0_set_bypass_mode(adev, gate);
if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
return 0; return 0;
if (state == AMD_CG_STATE_GATE)
gate = true;
uvd_v4_2_enable_mgcg(adev, gate); uvd_v4_2_enable_mgcg(adev, gate);
return 0; return 0;