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[PATCH] dvb: frontend: s5h1420: fixes 

Misc. fixes.

Signed-off-by: Andrew de Quincey <adq_dvb@lidskialf.net>
Signed-off-by: Johannes Stezenbach <js@linuxtv.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Andrew de Quincey 2005-09-09 13:02:31 -07:00 committed by Linus Torvalds
parent cfbfce1566
commit a9d6a80b41
3 changed files with 97 additions and 69 deletions
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162
drivers/media/dvb/frontends/s5h1420.c
View File

@ -48,7 +48,8 @@ struct s5h1420_state {
}; };
static u32 s5h1420_getsymbolrate(struct s5h1420_state* state); static u32 s5h1420_getsymbolrate(struct s5h1420_state* state);
static int s5h1420_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings); static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
struct dvb_frontend_tune_settings* fesettings);
static int debug = 0; static int debug = 0;
@ -91,7 +92,8 @@ static int s5h1420_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltag
switch(voltage) { switch(voltage) {
case SEC_VOLTAGE_13: case SEC_VOLTAGE_13:
s5h1420_writereg(state, 0x3c, (s5h1420_readreg(state, 0x3c) & 0xfe) | 0x02); s5h1420_writereg(state, 0x3c,
(s5h1420_readreg(state, 0x3c) & 0xfe) | 0x02);
break; break;
case SEC_VOLTAGE_18: case SEC_VOLTAGE_18:
@ -112,18 +114,21 @@ static int s5h1420_set_tone (struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
switch(tone) { switch(tone) {
case SEC_TONE_ON: case SEC_TONE_ON:
s5h1420_writereg(state, 0x3b, (s5h1420_readreg(state, 0x3b) & 0x74) | 0x08); s5h1420_writereg(state, 0x3b,
(s5h1420_readreg(state, 0x3b) & 0x74) | 0x08);
break; break;
case SEC_TONE_OFF: case SEC_TONE_OFF:
s5h1420_writereg(state, 0x3b, (s5h1420_readreg(state, 0x3b) & 0x74) | 0x01); s5h1420_writereg(state, 0x3b,
(s5h1420_readreg(state, 0x3b) & 0x74) | 0x01);
break; break;
} }
return 0; return 0;
} }
static int s5h1420_send_master_cmd (struct dvb_frontend* fe, struct dvb_diseqc_master_cmd* cmd) static int s5h1420_send_master_cmd (struct dvb_frontend* fe,
struct dvb_diseqc_master_cmd* cmd)
{ {
struct s5h1420_state* state = fe->demodulator_priv; struct s5h1420_state* state = fe->demodulator_priv;
u8 val; u8 val;
@ -131,6 +136,9 @@ static int s5h1420_send_master_cmd (struct dvb_frontend* fe, struct dvb_diseqc_m
unsigned long timeout; unsigned long timeout;
int result = 0; int result = 0;
if (cmd->msg_len > 8)
return -EINVAL;
/* setup for DISEQC */ /* setup for DISEQC */
val = s5h1420_readreg(state, 0x3b); val = s5h1420_readreg(state, 0x3b);
s5h1420_writereg(state, 0x3b, 0x02); s5h1420_writereg(state, 0x3b, 0x02);
@ -138,16 +146,17 @@ static int s5h1420_send_master_cmd (struct dvb_frontend* fe, struct dvb_diseqc_m
/* write the DISEQC command bytes */ /* write the DISEQC command bytes */
for(i=0; i< cmd->msg_len; i++) { for(i=0; i< cmd->msg_len; i++) {
s5h1420_writereg(state, 0x3c + i, cmd->msg[i]); s5h1420_writereg(state, 0x3d + i, cmd->msg[i]);
} }
/* kick off transmission */ /* kick off transmission */
s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | ((cmd->msg_len-1) << 4) | 0x08); s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) |
((cmd->msg_len-1) << 4) | 0x08);
/* wait for transmission to complete */ /* wait for transmission to complete */
timeout = jiffies + ((100*HZ) / 1000); timeout = jiffies + ((100*HZ) / 1000);
while(time_before(jiffies, timeout)) { while(time_before(jiffies, timeout)) {
if (s5h1420_readreg(state, 0x3b) & 0x08) if (!(s5h1420_readreg(state, 0x3b) & 0x08))
break; break;
msleep(5); msleep(5);
@ -161,7 +170,8 @@ static int s5h1420_send_master_cmd (struct dvb_frontend* fe, struct dvb_diseqc_m
return result; return result;
} }
static int s5h1420_recv_slave_reply (struct dvb_frontend* fe, struct dvb_diseqc_slave_reply* reply) static int s5h1420_recv_slave_reply (struct dvb_frontend* fe,
struct dvb_diseqc_slave_reply* reply)
{ {
struct s5h1420_state* state = fe->demodulator_priv; struct s5h1420_state* state = fe->demodulator_priv;
u8 val; u8 val;
@ -205,7 +215,7 @@ static int s5h1420_recv_slave_reply (struct dvb_frontend* fe, struct dvb_diseqc_
/* extract data */ /* extract data */
for(i=0; i< length; i++) { for(i=0; i< length; i++) {
reply->msg[i] = s5h1420_readreg(state, 0x3c + i); reply->msg[i] = s5h1420_readreg(state, 0x3d + i);
} }
exit: exit:
@ -236,7 +246,7 @@ static int s5h1420_send_burst (struct dvb_frontend* fe, fe_sec_mini_cmd_t minicm
s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x08); s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x08);
/* wait for transmission to complete */ /* wait for transmission to complete */
timeout = jiffies + ((20*HZ) / 1000); timeout = jiffies + ((100*HZ) / 1000);
while(time_before(jiffies, timeout)) { while(time_before(jiffies, timeout)) {
if (!(s5h1420_readreg(state, 0x3b) & 0x08)) if (!(s5h1420_readreg(state, 0x3b) & 0x08))
break; break;
@ -259,9 +269,9 @@ static fe_status_t s5h1420_get_status_bits(struct s5h1420_state* state)
val = s5h1420_readreg(state, 0x14); val = s5h1420_readreg(state, 0x14);
if (val & 0x02) if (val & 0x02)
status |= FE_HAS_SIGNAL; // FIXME: not sure if this is right status |= FE_HAS_SIGNAL;
if (val & 0x01) if (val & 0x01)
status |= FE_HAS_CARRIER; // FIXME: not sure if this is right status |= FE_HAS_CARRIER;
val = s5h1420_readreg(state, 0x36); val = s5h1420_readreg(state, 0x36);
if (val & 0x01) if (val & 0x01)
status |= FE_HAS_VITERBI; status |= FE_HAS_VITERBI;
@ -284,8 +294,8 @@ static int s5h1420_read_status(struct dvb_frontend* fe, fe_status_t* status)
/* determine lock state */ /* determine lock state */
*status = s5h1420_get_status_bits(state); *status = s5h1420_get_status_bits(state);
/* fix for FEC 5/6 inversion issue - if it doesn't quite lock, invert the inversion, /* fix for FEC 5/6 inversion issue - if it doesn't quite lock, invert
wait a bit and check again */ the inversion, wait a bit and check again */
if (*status == (FE_HAS_SIGNAL|FE_HAS_CARRIER|FE_HAS_VITERBI)) { if (*status == (FE_HAS_SIGNAL|FE_HAS_CARRIER|FE_HAS_VITERBI)) {
val = s5h1420_readreg(state, 0x32); val = s5h1420_readreg(state, 0x32);
if ((val & 0x07) == 0x03) { if ((val & 0x07) == 0x03) {
@ -330,6 +340,10 @@ static int s5h1420_read_status(struct dvb_frontend* fe, fe_status_t* status)
tmp = (tmp * 2 * 7) / 8; tmp = (tmp * 2 * 7) / 8;
break; break;
} }
if (tmp == 0) {
printk("s5h1420: avoided division by 0\n");
tmp = 1;
}
tmp = state->fclk / tmp; tmp = state->fclk / tmp;
/* set the MPEG_CLK_INTL for the calculated data rate */ /* set the MPEG_CLK_INTL for the calculated data rate */
@ -368,16 +382,21 @@ static int s5h1420_read_ber(struct dvb_frontend* fe, u32* ber)
s5h1420_writereg(state, 0x46, 0x1d); s5h1420_writereg(state, 0x46, 0x1d);
mdelay(25); mdelay(25);
return (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
*ber = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
return 0;
} }
static int s5h1420_read_signal_strength(struct dvb_frontend* fe, u16* strength) static int s5h1420_read_signal_strength(struct dvb_frontend* fe, u16* strength)
{ {
struct s5h1420_state* state = fe->demodulator_priv; struct s5h1420_state* state = fe->demodulator_priv;
u8 val = 0xff - s5h1420_readreg(state, 0x15); u8 val = s5h1420_readreg(state, 0x15);
return (int) ((val << 8) | val); *strength = (u16) ((val << 8) | val);
return 0;
} }
static int s5h1420_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) static int s5h1420_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
@ -386,7 +405,10 @@ static int s5h1420_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
s5h1420_writereg(state, 0x46, 0x1f); s5h1420_writereg(state, 0x46, 0x1f);
mdelay(25); mdelay(25);
return (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
*ucblocks = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
return 0;
} }
static void s5h1420_reset(struct s5h1420_state* state) static void s5h1420_reset(struct s5h1420_state* state)
@ -396,11 +418,12 @@ static void s5h1420_reset(struct s5h1420_state* state)
udelay(10); udelay(10);
} }
static void s5h1420_setsymbolrate(struct s5h1420_state* state, struct dvb_frontend_parameters *p) static void s5h1420_setsymbolrate(struct s5h1420_state* state,
struct dvb_frontend_parameters *p)
{ {
u64 val; u64 val;
val = (p->u.qpsk.symbol_rate / 1000) * (1<<24); val = ((u64) p->u.qpsk.symbol_rate / 1000ULL) * (1ULL<<24);
if (p->u.qpsk.symbol_rate <= 21000000) { if (p->u.qpsk.symbol_rate <= 21000000) {
val *= 2; val *= 2;
} }
@ -415,7 +438,7 @@ static void s5h1420_setsymbolrate(struct s5h1420_state* state, struct dvb_fronte
static u32 s5h1420_getsymbolrate(struct s5h1420_state* state) static u32 s5h1420_getsymbolrate(struct s5h1420_state* state)
{ {
u64 val; u64 val = 0;
int sampling = 2; int sampling = 2;
if (s5h1420_readreg(state, 0x05) & 0x2) if (s5h1420_readreg(state, 0x05) & 0x2)
@ -427,10 +450,10 @@ static u32 s5h1420_getsymbolrate(struct s5h1420_state* state)
val |= s5h1420_readreg(state, 0x13); val |= s5h1420_readreg(state, 0x13);
s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7); s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7);
val *= (state->fclk / 1000); val *= (state->fclk / 1000ULL);
do_div(val, ((1<<24) * sampling)); do_div(val, ((1<<24) * sampling));
return (u32) (val * 1000); return (u32) (val * 1000ULL);
} }
static void s5h1420_setfreqoffset(struct s5h1420_state* state, int freqoffset) static void s5h1420_setfreqoffset(struct s5h1420_state* state, int freqoffset)
@ -463,46 +486,55 @@ static int s5h1420_getfreqoffset(struct s5h1420_state* state)
/* remember freqoffset is in kHz, but the chip wants the offset in Hz, so /* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
* divide fclk by 1000000 to get the correct value. */ * divide fclk by 1000000 to get the correct value. */
val = - ((val * (state->fclk/1000000)) / (1<<24)); val = (((-val) * (state->fclk/1000000)) / (1<<24));
return val; return val;
} }
static void s5h1420_setfec(struct s5h1420_state* state, struct dvb_frontend_parameters *p) static void s5h1420_setfec_inversion(struct s5h1420_state* state,
struct dvb_frontend_parameters *p)
{ {
u8 inversion = 0;
if (p->inversion == INVERSION_OFF) {
inversion = state->config->invert ? 0x08 : 0;
} else if (p->inversion == INVERSION_ON) {
inversion = state->config->invert ? 0 : 0x08;
}
if ((p->u.qpsk.fec_inner == FEC_AUTO) || (p->inversion == INVERSION_AUTO)) { if ((p->u.qpsk.fec_inner == FEC_AUTO) || (p->inversion == INVERSION_AUTO)) {
s5h1420_writereg(state, 0x31, 0x00);
s5h1420_writereg(state, 0x30, 0x3f); s5h1420_writereg(state, 0x30, 0x3f);
s5h1420_writereg(state, 0x31, 0x00 | inversion);
} else { } else {
switch(p->u.qpsk.fec_inner) { switch(p->u.qpsk.fec_inner) {
case FEC_1_2: case FEC_1_2:
s5h1420_writereg(state, 0x31, 0x10);
s5h1420_writereg(state, 0x30, 0x01); s5h1420_writereg(state, 0x30, 0x01);
s5h1420_writereg(state, 0x31, 0x10 | inversion);
break; break;
case FEC_2_3: case FEC_2_3:
s5h1420_writereg(state, 0x31, 0x11);
s5h1420_writereg(state, 0x30, 0x02); s5h1420_writereg(state, 0x30, 0x02);
s5h1420_writereg(state, 0x31, 0x11 | inversion);
break; break;
case FEC_3_4: case FEC_3_4:
s5h1420_writereg(state, 0x31, 0x12);
s5h1420_writereg(state, 0x30, 0x04); s5h1420_writereg(state, 0x30, 0x04);
break; s5h1420_writereg(state, 0x31, 0x12 | inversion);
break;
case FEC_5_6: case FEC_5_6:
s5h1420_writereg(state, 0x31, 0x13);
s5h1420_writereg(state, 0x30, 0x08); s5h1420_writereg(state, 0x30, 0x08);
s5h1420_writereg(state, 0x31, 0x13 | inversion);
break; break;
case FEC_6_7: case FEC_6_7:
s5h1420_writereg(state, 0x31, 0x14);
s5h1420_writereg(state, 0x30, 0x10); s5h1420_writereg(state, 0x30, 0x10);
s5h1420_writereg(state, 0x31, 0x14 | inversion);
break; break;
case FEC_7_8: case FEC_7_8:
s5h1420_writereg(state, 0x31, 0x15);
s5h1420_writereg(state, 0x30, 0x20); s5h1420_writereg(state, 0x30, 0x20);
s5h1420_writereg(state, 0x31, 0x15 | inversion);
break; break;
default: default:
@ -536,22 +568,6 @@ static fe_code_rate_t s5h1420_getfec(struct s5h1420_state* state)
return FEC_NONE; return FEC_NONE;
} }
static void s5h1420_setinversion(struct s5h1420_state* state, struct dvb_frontend_parameters *p)
{
if ((p->u.qpsk.fec_inner == FEC_AUTO) || (p->inversion == INVERSION_AUTO)) {
s5h1420_writereg(state, 0x31, 0x00);
s5h1420_writereg(state, 0x30, 0x3f);
} else {
u8 tmp = s5h1420_readreg(state, 0x31) & 0xf7;
tmp |= 0x10;
if (p->inversion == INVERSION_ON)
tmp |= 0x80;
s5h1420_writereg(state, 0x31, tmp);
}
}
static fe_spectral_inversion_t s5h1420_getinversion(struct s5h1420_state* state) static fe_spectral_inversion_t s5h1420_getinversion(struct s5h1420_state* state)
{ {
if (s5h1420_readreg(state, 0x32) & 0x08) if (s5h1420_readreg(state, 0x32) & 0x08)
@ -560,35 +576,35 @@ static fe_spectral_inversion_t s5h1420_getinversion(struct s5h1420_state* state)
return INVERSION_OFF; return INVERSION_OFF;
} }
static int s5h1420_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) static int s5h1420_set_frontend(struct dvb_frontend* fe,
struct dvb_frontend_parameters *p)
{ {
struct s5h1420_state* state = fe->demodulator_priv; struct s5h1420_state* state = fe->demodulator_priv;
u32 frequency_delta; int frequency_delta;
struct dvb_frontend_tune_settings fesettings; struct dvb_frontend_tune_settings fesettings;
u32 tmp;
/* check if we should do a fast-tune */ /* check if we should do a fast-tune */
memcpy(&fesettings.parameters, p, sizeof(struct dvb_frontend_parameters)); memcpy(&fesettings.parameters, p, sizeof(struct dvb_frontend_parameters));
s5h1420_get_tune_settings(fe, &fesettings); s5h1420_get_tune_settings(fe, &fesettings);
frequency_delta = p->frequency - state->tunedfreq; frequency_delta = p->frequency - state->tunedfreq;
if ((frequency_delta > -fesettings.max_drift) && (frequency_delta < fesettings.max_drift) && if ((frequency_delta > -fesettings.max_drift) &&
(frequency_delta < fesettings.max_drift) &&
(frequency_delta != 0) && (frequency_delta != 0) &&
(state->fec_inner == p->u.qpsk.fec_inner) && (state->fec_inner == p->u.qpsk.fec_inner) &&
(state->symbol_rate == p->u.qpsk.symbol_rate)) { (state->symbol_rate == p->u.qpsk.symbol_rate)) {
s5h1420_setfreqoffset(state, frequency_delta); if (state->config->pll_set) {
s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) | 1);
state->config->pll_set(fe, p, &tmp);
s5h1420_setfreqoffset(state, p->frequency - tmp);
}
return 0; return 0;
} }
/* first of all, software reset */ /* first of all, software reset */
s5h1420_reset(state); s5h1420_reset(state);
/* set tuner PLL */
if (state->config->pll_set) {
s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) | 1);
state->config->pll_set(fe, p, &state->tunedfreq);
s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) & 0xfe);
}
/* set s5h1420 fclk PLL according to desired symbol rate */ /* set s5h1420 fclk PLL according to desired symbol rate */
if (p->u.qpsk.symbol_rate > 28000000) { if (p->u.qpsk.symbol_rate > 28000000) {
state->fclk = 88000000; state->fclk = 88000000;
@ -609,8 +625,9 @@ static int s5h1420_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_par
/* set misc registers */ /* set misc registers */
s5h1420_writereg(state, 0x02, 0x00); s5h1420_writereg(state, 0x02, 0x00);
s5h1420_writereg(state, 0x06, 0x00);
s5h1420_writereg(state, 0x07, 0xb0); s5h1420_writereg(state, 0x07, 0xb0);
s5h1420_writereg(state, 0x0a, 0x67); s5h1420_writereg(state, 0x0a, 0xe7);
s5h1420_writereg(state, 0x0b, 0x78); s5h1420_writereg(state, 0x0b, 0x78);
s5h1420_writereg(state, 0x0c, 0x48); s5h1420_writereg(state, 0x0c, 0x48);
s5h1420_writereg(state, 0x0d, 0x6b); s5h1420_writereg(state, 0x0d, 0x6b);
@ -626,21 +643,26 @@ static int s5h1420_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_par
/* start QPSK */ /* start QPSK */
s5h1420_writereg(state, 0x05, s5h1420_readreg(state, 0x05) | 1); s5h1420_writereg(state, 0x05, s5h1420_readreg(state, 0x05) | 1);
/* set the frequency offset to adjust for PLL inaccuracy */ /* set tuner PLL */
s5h1420_setfreqoffset(state, p->frequency - state->tunedfreq); if (state->config->pll_set) {
s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) | 1);
state->config->pll_set(fe, p, &tmp);
s5h1420_setfreqoffset(state, 0);
}
/* set the reset of the parameters */ /* set the reset of the parameters */
s5h1420_setsymbolrate(state, p); s5h1420_setsymbolrate(state, p);
s5h1420_setinversion(state, p); s5h1420_setfec_inversion(state, p);
s5h1420_setfec(state, p);
state->fec_inner = p->u.qpsk.fec_inner; state->fec_inner = p->u.qpsk.fec_inner;
state->symbol_rate = p->u.qpsk.symbol_rate; state->symbol_rate = p->u.qpsk.symbol_rate;
state->postlocked = 0; state->postlocked = 0;
state->tunedfreq = p->frequency;
return 0; return 0;
} }
static int s5h1420_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) static int s5h1420_get_frontend(struct dvb_frontend* fe,
struct dvb_frontend_parameters *p)
{ {
struct s5h1420_state* state = fe->demodulator_priv; struct s5h1420_state* state = fe->demodulator_priv;
@ -652,7 +674,8 @@ static int s5h1420_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_par
return 0; return 0;
} }
static int s5h1420_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings) static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
struct dvb_frontend_tune_settings* fesettings)
{ {
if (fesettings->parameters.u.qpsk.symbol_rate > 20000000) { if (fesettings->parameters.u.qpsk.symbol_rate > 20000000) {
fesettings->min_delay_ms = 50; fesettings->min_delay_ms = 50;
@ -717,7 +740,8 @@ static void s5h1420_release(struct dvb_frontend* fe)
static struct dvb_frontend_ops s5h1420_ops; static struct dvb_frontend_ops s5h1420_ops;
struct dvb_frontend* s5h1420_attach(const struct s5h1420_config* config, struct i2c_adapter* i2c) struct dvb_frontend* s5h1420_attach(const struct s5h1420_config* config,
struct i2c_adapter* i2c)
{ {
struct s5h1420_state* state = NULL; struct s5h1420_state* state = NULL;
u8 identity; u8 identity;

3
drivers/media/dvb/frontends/s5h1420.h
View File

@ -30,6 +30,9 @@ struct s5h1420_config
/* the demodulator's i2c address */ /* the demodulator's i2c address */
u8 demod_address; u8 demod_address;
/* does the inversion require inversion? */
u8 invert:1;
/* PLL maintenance */ /* PLL maintenance */
int (*pll_init)(struct dvb_frontend* fe); int (*pll_init)(struct dvb_frontend* fe);
int (*pll_set)(struct dvb_frontend* fe, struct dvb_frontend_parameters* params, u32* freqout); int (*pll_set)(struct dvb_frontend* fe, struct dvb_frontend_parameters* params, u32* freqout);

1
drivers/media/dvb/ttpci/budget.c
View File

@ -480,6 +480,7 @@ static int s5h1420_pll_set(struct dvb_frontend* fe, struct dvb_frontend_paramete
static struct s5h1420_config s5h1420_config = { static struct s5h1420_config s5h1420_config = {
.demod_address = 0x53, .demod_address = 0x53,
.invert = 1,
.pll_set = s5h1420_pll_set, .pll_set = s5h1420_pll_set,
}; };