net/mlx5: FPGA, Add SBU infrastructure
Add interface to initialize and interact with Innova FPGA SBU connections. A client driver may use these functions to set up a high-speed DMA connection with its SBU hardware logic, and send/receive messages over this connection. A later patch in this patchset will make use of these functions for Innova IPSec offload in mlx5 Ethernet driver. Add commands to retrieve Innova FPGA SBU capabilities, and to read/write Innova FPGA configuration space registers and memory, over internal I2C. At high level, the FPGA configuration space is divided such: 0x00000000 - 0x007fffff is reserved for the SBU 0x00800000 - 0xffffffff is reserved for the Shell 0x400000000 - ... is DDR memory A later patchset will add support for accessing FPGA CrSpace and memory over a high-speed connection. This is the reason for the ACCESS_TYPE enumeration, which currently only supports I2C. Signed-off-by: Ilan Tayari <ilant@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
This commit is contained in:
Ilan Tayari
Saeed Mahameed
parent
c43051d72a
commit
a9956d35d1
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@ -6,7 +6,7 @@ mlx5_core-y := main.o cmd.o debugfs.o fw.o eq.o uar.o pagealloc.o \
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mad.o transobj.o vport.o sriov.o fs_cmd.o fs_core.o \
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fs_counters.o rl.o lag.o dev.o lib/gid.o
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mlx5_core-$(CONFIG_MLX5_FPGA) += fpga/cmd.o fpga/core.o fpga/conn.o
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mlx5_core-$(CONFIG_MLX5_FPGA) += fpga/cmd.o fpga/core.o fpga/conn.o fpga/sdk.o
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mlx5_core-$(CONFIG_MLX5_CORE_EN) += wq.o eswitch.o eswitch_offloads.o \
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en_main.o en_common.o en_fs.o en_ethtool.o en_tx.o \
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@ -38,6 +38,39 @@
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#include "mlx5_core.h"
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#include "fpga/cmd.h"
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#define MLX5_FPGA_ACCESS_REG_SZ (MLX5_ST_SZ_DW(fpga_access_reg) + \
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MLX5_FPGA_ACCESS_REG_SIZE_MAX)
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int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr,
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void *buf, bool write)
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{
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u32 in[MLX5_FPGA_ACCESS_REG_SZ] = {0};
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u32 out[MLX5_FPGA_ACCESS_REG_SZ];
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int err;
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if (size & 3)
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return -EINVAL;
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if (addr & 3)
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return -EINVAL;
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if (size > MLX5_FPGA_ACCESS_REG_SIZE_MAX)
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return -EINVAL;
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MLX5_SET(fpga_access_reg, in, size, size);
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MLX5_SET64(fpga_access_reg, in, address, addr);
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if (write)
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memcpy(MLX5_ADDR_OF(fpga_access_reg, in, data), buf, size);
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err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
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MLX5_REG_FPGA_ACCESS_REG, 0, write);
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if (err)
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return err;
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if (!write)
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memcpy(buf, MLX5_ADDR_OF(fpga_access_reg, out, data), size);
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return 0;
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}
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int mlx5_fpga_caps(struct mlx5_core_dev *dev, u32 *caps)
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{
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u32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0};
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@ -58,6 +91,38 @@ int mlx5_fpga_ctrl_op(struct mlx5_core_dev *dev, u8 op)
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MLX5_REG_FPGA_CTRL, 0, true);
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}
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int mlx5_fpga_sbu_caps(struct mlx5_core_dev *dev, void *caps, int size)
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{
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unsigned int cap_size = MLX5_CAP_FPGA(dev, sandbox_extended_caps_len);
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u64 addr = MLX5_CAP64_FPGA(dev, sandbox_extended_caps_addr);
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unsigned int read;
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int ret = 0;
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if (cap_size > size) {
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mlx5_core_warn(dev, "Not enough buffer %u for FPGA SBU caps %u",
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size, cap_size);
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return -EINVAL;
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}
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while (cap_size > 0) {
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read = min_t(unsigned int, cap_size,
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MLX5_FPGA_ACCESS_REG_SIZE_MAX);
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ret = mlx5_fpga_access_reg(dev, read, addr, caps, false);
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if (ret) {
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mlx5_core_warn(dev, "Error reading FPGA SBU caps %u bytes at address 0x%llx: %d",
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read, addr, ret);
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return ret;
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}
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cap_size -= read;
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addr += read;
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caps += read;
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}
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return ret;
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}
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int mlx5_fpga_query(struct mlx5_core_dev *dev, struct mlx5_fpga_query *query)
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{
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u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
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@ -68,6 +68,9 @@ struct mlx5_fpga_qp_counters {
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int mlx5_fpga_caps(struct mlx5_core_dev *dev, u32 *caps);
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int mlx5_fpga_query(struct mlx5_core_dev *dev, struct mlx5_fpga_query *query);
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int mlx5_fpga_ctrl_op(struct mlx5_core_dev *dev, u8 op);
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int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr,
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void *buf, bool write);
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int mlx5_fpga_sbu_caps(struct mlx5_core_dev *dev, void *caps, int size);
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int mlx5_fpga_create_qp(struct mlx5_core_dev *dev, void *fpga_qpc,
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u32 *fpga_qpn);
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@ -0,0 +1,164 @@
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/*
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* Copyright (c) 2017 Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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#include <linux/mlx5/device.h>
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#include "fpga/core.h"
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#include "fpga/conn.h"
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#include "fpga/sdk.h"
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struct mlx5_fpga_conn *
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mlx5_fpga_sbu_conn_create(struct mlx5_fpga_device *fdev,
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struct mlx5_fpga_conn_attr *attr)
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{
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return mlx5_fpga_conn_create(fdev, attr, MLX5_FPGA_QPC_QP_TYPE_SANDBOX_QP);
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}
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EXPORT_SYMBOL(mlx5_fpga_sbu_conn_create);
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void mlx5_fpga_sbu_conn_destroy(struct mlx5_fpga_conn *conn)
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{
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mlx5_fpga_conn_destroy(conn);
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}
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EXPORT_SYMBOL(mlx5_fpga_sbu_conn_destroy);
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int mlx5_fpga_sbu_conn_sendmsg(struct mlx5_fpga_conn *conn,
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struct mlx5_fpga_dma_buf *buf)
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{
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return mlx5_fpga_conn_send(conn, buf);
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}
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EXPORT_SYMBOL(mlx5_fpga_sbu_conn_sendmsg);
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static int mlx5_fpga_mem_read_i2c(struct mlx5_fpga_device *fdev, size_t size,
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u64 addr, u8 *buf)
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{
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size_t max_size = MLX5_FPGA_ACCESS_REG_SIZE_MAX;
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size_t bytes_done = 0;
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u8 actual_size;
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int err;
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if (!fdev->mdev)
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return -ENOTCONN;
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while (bytes_done < size) {
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actual_size = min(max_size, (size - bytes_done));
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err = mlx5_fpga_access_reg(fdev->mdev, actual_size,
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addr + bytes_done,
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buf + bytes_done, false);
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if (err) {
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mlx5_fpga_err(fdev, "Failed to read over I2C: %d\n",
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err);
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break;
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}
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bytes_done += actual_size;
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}
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return err;
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}
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static int mlx5_fpga_mem_write_i2c(struct mlx5_fpga_device *fdev, size_t size,
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u64 addr, u8 *buf)
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{
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size_t max_size = MLX5_FPGA_ACCESS_REG_SIZE_MAX;
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size_t bytes_done = 0;
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u8 actual_size;
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int err;
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if (!fdev->mdev)
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return -ENOTCONN;
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while (bytes_done < size) {
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actual_size = min(max_size, (size - bytes_done));
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err = mlx5_fpga_access_reg(fdev->mdev, actual_size,
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addr + bytes_done,
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buf + bytes_done, true);
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if (err) {
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mlx5_fpga_err(fdev, "Failed to write FPGA crspace\n");
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break;
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}
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bytes_done += actual_size;
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}
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return err;
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}
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int mlx5_fpga_mem_read(struct mlx5_fpga_device *fdev, size_t size, u64 addr,
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void *buf, enum mlx5_fpga_access_type access_type)
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{
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int ret;
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switch (access_type) {
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case MLX5_FPGA_ACCESS_TYPE_I2C:
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ret = mlx5_fpga_mem_read_i2c(fdev, size, addr, buf);
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if (ret)
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return ret;
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break;
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default:
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mlx5_fpga_warn(fdev, "Unexpected read access_type %u\n",
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access_type);
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return -EACCES;
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}
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return size;
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}
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EXPORT_SYMBOL(mlx5_fpga_mem_read);
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int mlx5_fpga_mem_write(struct mlx5_fpga_device *fdev, size_t size, u64 addr,
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void *buf, enum mlx5_fpga_access_type access_type)
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{
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int ret;
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switch (access_type) {
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case MLX5_FPGA_ACCESS_TYPE_I2C:
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ret = mlx5_fpga_mem_write_i2c(fdev, size, addr, buf);
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if (ret)
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return ret;
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break;
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default:
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mlx5_fpga_warn(fdev, "Unexpected write access_type %u\n",
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access_type);
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return -EACCES;
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}
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return size;
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}
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EXPORT_SYMBOL(mlx5_fpga_mem_write);
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int mlx5_fpga_get_sbu_caps(struct mlx5_fpga_device *fdev, int size, void *buf)
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{
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return mlx5_fpga_sbu_caps(fdev->mdev, buf, size);
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}
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EXPORT_SYMBOL(mlx5_fpga_get_sbu_caps);
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@ -42,6 +42,11 @@
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* This header defines the in-kernel API for Innova FPGA client drivers.
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*/
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enum mlx5_fpga_access_type {
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MLX5_FPGA_ACCESS_TYPE_I2C = 0x0,
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MLX5_FPGA_ACCESS_TYPE_DONTCARE = 0x0,
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};
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struct mlx5_fpga_conn;
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struct mlx5_fpga_device;
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@ -103,4 +108,97 @@ struct mlx5_fpga_conn_attr {
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void *cb_arg;
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};
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/**
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* mlx5_fpga_sbu_conn_create() - Initialize a new FPGA SBU connection
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* @fdev: The FPGA device
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* @attr: Attributes of the new connection
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*
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* Sets up a new FPGA SBU connection with the specified attributes.
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* The receive callback function may be called for incoming messages even
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* before this function returns.
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*
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* The caller must eventually destroy the connection by calling
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* mlx5_fpga_sbu_conn_destroy.
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*
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* Return: A new connection, or ERR_PTR() error value otherwise.
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*/
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struct mlx5_fpga_conn *
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mlx5_fpga_sbu_conn_create(struct mlx5_fpga_device *fdev,
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struct mlx5_fpga_conn_attr *attr);
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/**
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* mlx5_fpga_sbu_conn_destroy() - Destroy an FPGA SBU connection
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* @conn: The FPGA SBU connection to destroy
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*
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* Cleans up an FPGA SBU connection which was previously created with
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* mlx5_fpga_sbu_conn_create.
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*/
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void mlx5_fpga_sbu_conn_destroy(struct mlx5_fpga_conn *conn);
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/**
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* mlx5_fpga_sbu_conn_sendmsg() - Queue the transmission of a packet
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* @fdev: An FPGA SBU connection
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* @buf: The packet buffer
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*
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* Queues a packet for transmission over an FPGA SBU connection.
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* The buffer should not be modified or freed until completion.
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* Upon completion, the buf's complete() callback is invoked, indicating the
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* success or error status of the transmission.
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*
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* Return: 0 if successful, or an error value otherwise.
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*/
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int mlx5_fpga_sbu_conn_sendmsg(struct mlx5_fpga_conn *conn,
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struct mlx5_fpga_dma_buf *buf);
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/**
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* mlx5_fpga_mem_read() - Read from FPGA memory address space
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* @fdev: The FPGA device
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* @size: Size of chunk to read, in bytes
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* @addr: Starting address to read from, in FPGA address space
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* @buf: Buffer to read into
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* @access_type: Method for reading
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*
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* Reads from the specified address into the specified buffer.
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* The address may point to configuration space or to DDR.
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* Large reads may be performed internally as several non-atomic operations.
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* This function may sleep, so should not be called from atomic contexts.
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*
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* Return: 0 if successful, or an error value otherwise.
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*/
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int mlx5_fpga_mem_read(struct mlx5_fpga_device *fdev, size_t size, u64 addr,
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void *buf, enum mlx5_fpga_access_type access_type);
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/**
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* mlx5_fpga_mem_write() - Write to FPGA memory address space
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* @fdev: The FPGA device
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* @size: Size of chunk to write, in bytes
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* @addr: Starting address to write to, in FPGA address space
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* @buf: Buffer which contains data to write
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* @access_type: Method for writing
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*
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* Writes the specified buffer data to FPGA memory at the specified address.
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* The address may point to configuration space or to DDR.
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* Large writes may be performed internally as several non-atomic operations.
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* This function may sleep, so should not be called from atomic contexts.
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*
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* Return: 0 if successful, or an error value otherwise.
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*/
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int mlx5_fpga_mem_write(struct mlx5_fpga_device *fdev, size_t size, u64 addr,
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void *buf, enum mlx5_fpga_access_type access_type);
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/**
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* mlx5_fpga_get_sbu_caps() - Read the SBU capabilities
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* @fdev: The FPGA device
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* @size: Size of the buffer to read into
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* @buf: Buffer to read the capabilities into
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*
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* Reads the FPGA SBU capabilities into the specified buffer.
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* The format of the capabilities buffer is SBU-dependent.
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*
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* Return: 0 if successful
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* -EINVAL if the buffer is not large enough to contain SBU caps
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* or any other error value otherwise.
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*/
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int mlx5_fpga_get_sbu_caps(struct mlx5_fpga_device *fdev, int size, void *buf);
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#endif /* MLX5_FPGA_SDK_H */
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@ -1103,6 +1103,9 @@ enum mlx5_mcam_feature_groups {
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#define MLX5_CAP_FPGA(mdev, cap) \
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MLX5_GET(fpga_cap, (mdev)->caps.hca_cur[MLX5_CAP_FPGA], cap)
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#define MLX5_CAP64_FPGA(mdev, cap) \
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MLX5_GET64(fpga_cap, (mdev)->caps.hca_cur[MLX5_CAP_FPGA], cap)
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enum {
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MLX5_CMD_STAT_OK = 0x0,
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MLX5_CMD_STAT_INT_ERR = 0x1,
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@ -111,6 +111,7 @@ enum {
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MLX5_REG_DCBX_APP = 0x4021,
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MLX5_REG_FPGA_CAP = 0x4022,
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MLX5_REG_FPGA_CTRL = 0x4023,
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MLX5_REG_FPGA_ACCESS_REG = 0x4024,
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MLX5_REG_PCAP = 0x5001,
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MLX5_REG_PMTU = 0x5003,
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MLX5_REG_PTYS = 0x5004,
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@ -8309,6 +8309,7 @@ union mlx5_ifc_ports_control_registers_document_bits {
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struct mlx5_ifc_sltp_reg_bits sltp_reg;
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struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
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struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
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struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
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struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
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struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
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struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
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@ -150,6 +150,19 @@ struct mlx5_ifc_fpga_error_event_bits {
|
|||
u8 reserved_at_60[0x80];
|
||||
};
|
||||
|
||||
#define MLX5_FPGA_ACCESS_REG_SIZE_MAX 64
|
||||
|
||||
struct mlx5_ifc_fpga_access_reg_bits {
|
||||
u8 reserved_at_0[0x20];
|
||||
|
||||
u8 reserved_at_20[0x10];
|
||||
u8 size[0x10];
|
||||
|
||||
u8 address[0x40];
|
||||
|
||||
u8 data[0][0x8];
|
||||
};
|
||||
|
||||
enum mlx5_ifc_fpga_qp_state {
|
||||
MLX5_FPGA_QPC_STATE_INIT = 0x0,
|
||||
MLX5_FPGA_QPC_STATE_ACTIVE = 0x1,
|
||||
|
|
|
|||
Loading…
Reference in New Issue