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drm/amdgpu/vcn: improve code indentation and alignment 

General code indentation and alignment changes such as replace spaces
by tabs or align function arguments as per the coding style
guidelines. Issue reported by checkpatch script.

Signed-off-by: Deepak R Varma <mh12gx2825@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Deepak R Varma 2020-11-02 22:48:21 +05:30 committed by Alex Deucher
parent 99dac206b0
commit a971887e02
3 changed files with 7 additions and 7 deletions
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2
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
View File

@ -45,7 +45,7 @@
#define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d
#define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x1e1 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x1e1
#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x5a6 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x5a6
#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x5a7 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x5a7
#define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x1e2 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x1e2

2
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
View File

@ -45,7 +45,7 @@
#define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431
#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4
#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5
#define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c
#define VCN25_MAX_HW_INSTANCES_ARCTURUS 2 #define VCN25_MAX_HW_INSTANCES_ARCTURUS 2

10
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
View File

@ -44,10 +44,10 @@
#define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431
#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4
#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5
#define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c
#define VCN_INSTANCES_SIENNA_CICHLID 2 #define VCN_INSTANCES_SIENNA_CICHLID 2
static int amdgpu_ih_clientid_vcns[] = { static int amdgpu_ih_clientid_vcns[] = {
SOC15_IH_CLIENTID_VCN, SOC15_IH_CLIENTID_VCN,
@ -55,8 +55,8 @@ static int amdgpu_ih_clientid_vcns[] = {
}; };
static int amdgpu_ucode_id_vcns[] = { static int amdgpu_ucode_id_vcns[] = {
AMDGPU_UCODE_ID_VCN, AMDGPU_UCODE_ID_VCN,
AMDGPU_UCODE_ID_VCN1 AMDGPU_UCODE_ID_VCN1
}; };
static int vcn_v3_0_start_sriov(struct amdgpu_device *adev); static int vcn_v3_0_start_sriov(struct amdgpu_device *adev);
@ -1371,7 +1371,7 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)
} }
/* Update init table header in memory */ /* Update init table header in memory */
size = sizeof(struct mmsch_v3_0_init_header); size = sizeof(struct mmsch_v3_0_init_header);
table_loc = (uint32_t *)table->cpu_addr; table_loc = (uint32_t *)table->cpu_addr;
memcpy((void *)table_loc, &header, size); memcpy((void *)table_loc, &header, size);