perf/x86/intel: Clean up SNB PEBS quirk
Clean up SNB PEBS quirk to use the new facility to check for min microcode revisions. Only check the boot CPU, assuming models and features are consistent over all CPUs. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: David Ahern <dsahern@gmail.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Cc: bp@alien8.de Link: https://lkml.kernel.org/r/1549319013-4522-3-git-send-email-kan.liang@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -3792,36 +3792,21 @@ static __init void intel_pebs_isolation_quirk(void)
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intel_check_pebs_isolation();
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}
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static int intel_snb_pebs_broken(int cpu)
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static const struct x86_cpu_desc pebs_ucodes[] = {
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INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028),
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INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618),
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INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c),
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{}
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};
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static bool intel_snb_pebs_broken(void)
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{
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u32 rev = UINT_MAX; /* default to broken for unknown models */
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switch (cpu_data(cpu).x86_model) {
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case INTEL_FAM6_SANDYBRIDGE:
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rev = 0x28;
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break;
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case INTEL_FAM6_SANDYBRIDGE_X:
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switch (cpu_data(cpu).x86_stepping) {
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case 6: rev = 0x618; break;
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case 7: rev = 0x70c; break;
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}
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}
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return (cpu_data(cpu).microcode < rev);
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return !x86_cpu_has_min_microcode_rev(pebs_ucodes);
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}
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static void intel_snb_check_microcode(void)
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{
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int pebs_broken = 0;
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int cpu;
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for_each_online_cpu(cpu) {
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if ((pebs_broken = intel_snb_pebs_broken(cpu)))
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break;
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}
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if (pebs_broken == x86_pmu.pebs_broken)
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if (intel_snb_pebs_broken() == x86_pmu.pebs_broken)
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return;
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/*
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