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arm64: dts: ti: k3-j721s2: Fix gic-v3 compatible regs 

Though GIC ARE option is disabled for no GIC-v2 compatibility,
Cortex-A72 is free to implement the CPU interface as long as it
communicates with the GIC using the stream protocol. This requires
that the SoC integration mark out the PERIPHBASE[1] as reserved area
within the SoC. See longer discussion in [2] for further information.

Update the GIC register map to indicate offsets from PERIPHBASE based
on [3]. Without doing this, systems like kvm will not function with
gic-v2 emulation.

[1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1
[2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/
[3] https://developer.arm.com/documentation/100095/0002/way1382452674438

Cc: stable@vger.kernel.org
Fixes: b8545f9d3a ("arm64: dts: ti: Add initial support for J721S2 SoC")
Reported-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220215201008.15235-6-nm@ti.com
This commit is contained in:
Nishanth Menon 2022-02-15 14:10:08 -06:00
parent de60edf1be
commit a966803781
2 changed files with 5 additions and 1 deletions
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5
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
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@ -34,7 +34,10 @@
#interrupt-cells = <3>; #interrupt-cells = <3>;
interrupt-controller; interrupt-controller;
reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */ reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */
<0x00 0x01900000 0x00 0x100000>; /* GICR */ <0x00 0x01900000 0x00 0x100000>, /* GICR */
<0x00 0x6f000000 0x00 0x2000>, /* GICC */
<0x00 0x6f010000 0x00 0x1000>, /* GICH */
<0x00 0x6f020000 0x00 0x2000>; /* GICV */
/* vcpumntirq: virtual CPU interface maintenance interrupt */ /* vcpumntirq: virtual CPU interface maintenance interrupt */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

1
arch/arm64/boot/dts/ti/k3-j721s2.dtsi
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@ -119,6 +119,7 @@
<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
<0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */ <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
<0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */ <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
<0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */ <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */