ARM: dts: qcom: Add ADM DMA + NAND definitions to ipq806x
Now the ADM driver is in mainline add the appropriate definitions for it and the NAND controller to get NAND working on IPQ806x platforms, Signed-off-by: Jonathan McDowell <noodles@earth.li> Link: https://lore.kernel.org/r/17f88a26860f5976ad08dd3c12ea079ba474b6fd.1621531633.git.noodles@earth.li Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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@ -185,6 +185,31 @@
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bias-pull-up;
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};
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};
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nand_pins: nand_pins {
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mux {
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pins = "gpio34", "gpio35", "gpio36",
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"gpio37", "gpio38", "gpio39",
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"gpio40", "gpio41", "gpio42",
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"gpio43", "gpio44", "gpio45",
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"gpio46", "gpio47";
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function = "nand";
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drive-strength = <10>;
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bias-disable;
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};
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pullups {
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pins = "gpio39";
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bias-pull-up;
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};
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hold {
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pins = "gpio40", "gpio41", "gpio42",
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"gpio43", "gpio44", "gpio45",
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"gpio46", "gpio47";
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bias-bus-hold;
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};
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};
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};
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intc: interrupt-controller@2000000 {
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@ -226,6 +251,26 @@
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reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
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};
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adm_dma: dma-controller@18300000 {
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compatible = "qcom,adm";
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reg = <0x18300000 0x100000>;
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interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
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clock-names = "core", "iface";
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resets = <&gcc ADM0_RESET>,
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<&gcc ADM0_PBUS_RESET>,
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<&gcc ADM0_C0_RESET>,
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<&gcc ADM0_C1_RESET>,
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<&gcc ADM0_C2_RESET>;
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reset-names = "clk", "pbus", "c0", "c1", "c2";
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qcom,ee = <0>;
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status = "disabled";
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};
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saw0: regulator@2089000 {
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compatible = "qcom,saw2";
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reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
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@ -403,6 +448,28 @@
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status = "disabled";
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};
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nand: nand-controller@1ac00000 {
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compatible = "qcom,ipq806x-nand";
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reg = <0x1ac00000 0x800>;
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pinctrl-0 = <&nand_pins>;
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pinctrl-names = "default";
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clocks = <&gcc EBI2_CLK>,
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<&gcc EBI2_AON_CLK>;
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clock-names = "core", "aon";
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dmas = <&adm_dma 3>;
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dma-names = "rxtx";
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qcom,cmd-crci = <15>;
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qcom,data-crci = <3>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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sata: sata@29000000 {
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compatible = "qcom,ipq806x-ahci", "generic-ahci";
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reg = <0x29000000 0x180>;
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