dt-bindings: devfreq: rk3399_dmc: Add more disable-freq properties
DDR DVFS tuning has found that several power-saving features don't have good tradeoffs at higher frequencies -- at higher frequencies, we'll see glitches or other errors. Provide tuning controls so these can be disabled at higher OPPs, and left active only at the lower ones. Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
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@ -313,6 +313,38 @@ properties:
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self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
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if bus is idle for standby_idle nanoseconds.
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rockchip,pd-idle-dis-freq-hz:
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description:
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Defines the power-down idle disable frequency in Hz. When the DDR
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frequency is greater than pd-idle-dis-freq, power-down idle is disabled.
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See also rockchip,pd-idle-ns.
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rockchip,sr-idle-dis-freq-hz:
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description:
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Defines the self-refresh idle disable frequency in Hz. When the DDR
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frequency is greater than sr-idle-dis-freq, self-refresh idle is
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disabled. See also rockchip,sr-idle-ns.
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rockchip,sr-mc-gate-idle-dis-freq-hz:
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description:
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Defines the self-refresh and memory-controller clock gating disable
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frequency in Hz. When the DDR frequency is greater than
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sr-mc-gate-idle-dis-freq, the clock will not be gated when idle. See also
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rockchip,sr-mc-gate-idle-ns.
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rockchip,srpd-lite-idle-dis-freq-hz:
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description:
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Defines the self-refresh power down idle disable frequency in Hz. When
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the DDR frequency is greater than srpd-lite-idle-dis-freq, memory will
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not be placed into self-refresh power down mode when idle. See also
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rockchip,srpd-lite-idle-ns.
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rockchip,standby-idle-dis-freq-hz:
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description:
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Defines the standby idle disable frequency in Hz. When the DDR frequency
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is greater than standby-idle-dis-freq, standby idle is disabled. See also
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rockchip,standby-idle-ns.
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required:
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- compatible
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- devfreq-events
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@ -344,4 +376,9 @@ examples:
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rockchip,ddr3_odt_dis_freq = <333000000>;
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rockchip,lpddr3_odt_dis_freq = <333000000>;
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rockchip,lpddr4_odt_dis_freq = <333000000>;
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rockchip,pd-idle-dis-freq-hz = <1000000000>;
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rockchip,sr-idle-dis-freq-hz = <1000000000>;
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rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>;
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rockchip,srpd-lite-idle-dis-freq-hz = <0>;
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rockchip,standby-idle-dis-freq-hz = <928000000>;
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};
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