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arm64: tegra: Device tree changes for v5.17-rc1 

The vast majority of this contains various updates and cleanups to the
 Tegra device trees that will eventually help validate all of them using
 the dt-schema infrastructure.
 
 Another notable chunk of this contains additional Tegra234 support as
 well as support for the new Jetson AGX Orin Developer Kit.
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Merge tag 'tegra-for-5.17-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

arm64: tegra: Device tree changes for v5.17-rc1

The vast majority of this contains various updates and cleanups to the
Tegra device trees that will eventually help validate all of them using
the dt-schema infrastructure.

Another notable chunk of this contains additional Tegra234 support as
well as support for the new Jetson AGX Orin Developer Kit.

* tag 'tegra-for-5.17-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (47 commits)
  arm64: tegra: Add host1x hotflush reset on Tegra210
  arm64: tegra: Hook up MMC and BPMP to memory controller
  arm64: tegra: Add memory controller on Tegra234
  arm64: tegra: Add EMC general interrupt on Tegra194
  arm64: tegra: Update SDMMC4 speeds for Tegra194
  arm64: tegra: Add dma-coherent for Tegra194 VIC
  arm64: tegra: Rename Ethernet PHY nodes
  arm64: tegra: Remove unused only-1-8-v properties
  arm64: tegra: Sort Tegra210 XUSB clocks correctly
  arm64: tegra: Add missing TSEC properties on Tegra210
  arm64: tegra: jetson-nano: Remove extra PLL power supplies for PCIe and XUSB
  arm64: tegra: smaug: Remove extra PLL power supplies for XUSB
  arm64: tegra: jetson-tx1: Remove extra PLL power supplies for PCIe and XUSB
  arm64: tegra: Rename GPIO hog nodes to match schema
  arm64: tegra: Remove unsupported regulator properties
  arm64: tegra: Rename TCU node to "serial"
  arm64: tegra: Remove undocumented Tegra194 PCIe "core_m" clock
  arm64: tegra: Drop unused properties for Tegra194 PCIe
  arm64: tegra: Fix Tegra194 HSP compatible string
  arm64: tegra: Drop unsupported nvidia,lpdr property
  ...

Link: https://lore.kernel.org/r/20211217162253.1801077-4-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2021-12-20 15:49:16 +01:00
parent b87cd3759d 914ed1f565
commit a862e81808
27 changed files with 1463 additions and 291 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm64/boot/dts/nvidia/Makefile
View File

@ -12,3 +12,4 @@ dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb
dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0000.dtb
dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0001.dtb
dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-sim-vdk.dtb
dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0000.dtb

36
arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
View File

@ -564,7 +564,7 @@
pinctrl-names = "default";
pinctrl-0 = <&as3722_default>;
as3722_default: pinmux@0 {
as3722_default: pinmux {
gpio0 {
pins = "gpio0";
function = "gpio";
@ -770,7 +770,7 @@
google,remote-bus = <0>;
charger: bq24735 {
charger: bq24735@9 {
compatible = "ti,bq24735";
reg = <0x9>;
interrupt-parent = <&gpio>;
@ -781,7 +781,7 @@
GPIO_ACTIVE_HIGH>;
};
battery: smart-battery {
battery: smart-battery@b {
compatible = "sbs,sbs-battery";
reg = <0xb>;
sbs,i2c-retry-count = <2>;
@ -885,14 +885,12 @@
pmc@7000e400 {
nvidia,invert-interrupt;
nvidia,suspend-mode = <0>;
#wake-cells = <3>;
nvidia,cpu-pwr-good-time = <500>;
nvidia,cpu-pwr-off-time = <300>;
nvidia,core-pwr-good-time = <641 3845>;
nvidia,core-pwr-off-time = <61036>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
nvidia,reset-gpio = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
};
usb@70090000 {
@ -1023,7 +1021,7 @@
default-brightness-level = <6>;
};
clk32k_in: clock@0 {
clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
@ -1057,7 +1055,7 @@
ddc-i2c-bus = <&dpaux>;
};
vdd_mux: regulator@0 {
vdd_mux: regulator-vdd-mux {
compatible = "regulator-fixed";
regulator-name = "+VDD_MUX";
regulator-min-microvolt = <19000000>;
@ -1066,7 +1064,7 @@
regulator-boot-on;
};
vdd_5v0_sys: regulator@1 {
vdd_5v0_sys: regulator-vdd-5v0-sys {
compatible = "regulator-fixed";
regulator-name = "+5V_SYS";
regulator-min-microvolt = <5000000>;
@ -1076,7 +1074,7 @@
vin-supply = <&vdd_mux>;
};
vdd_3v3_sys: regulator@2 {
vdd_3v3_sys: regulator-vdd-3v3-sys {
compatible = "regulator-fixed";
regulator-name = "+3.3V_SYS";
regulator-min-microvolt = <3300000>;
@ -1086,7 +1084,7 @@
vin-supply = <&vdd_mux>;
};
vdd_3v3_run: regulator@3 {
vdd_3v3_run: regulator-vdd-3v3-run {
compatible = "regulator-fixed";
regulator-name = "+3.3V_RUN";
regulator-min-microvolt = <3300000>;
@ -1098,7 +1096,7 @@
vin-supply = <&vdd_3v3_sys>;
};
vdd_3v3_hdmi: regulator@4 {
vdd_3v3_hdmi: regulator-vdd-3v3-hdmi {
compatible = "regulator-fixed";
regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
regulator-min-microvolt = <3300000>;
@ -1106,7 +1104,7 @@
vin-supply = <&vdd_3v3_run>;
};
vdd_led: regulator@5 {
vdd_led: regulator-vdd-led {
compatible = "regulator-fixed";
regulator-name = "+VDD_LED";
regulator-min-microvolt = <3300000>;
@ -1116,7 +1114,7 @@
vin-supply = <&vdd_mux>;
};
vdd_usb1_vbus: regulator@6 {
vdd_usb1_vbus: regulator-vdd-usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "+5V_USB_HS";
regulator-min-microvolt = <5000000>;
@ -1127,7 +1125,7 @@
vin-supply = <&vdd_5v0_sys>;
};
vdd_usb3_vbus: regulator@7 {
vdd_usb3_vbus: regulator-vdd-usb3-vbus {
compatible = "regulator-fixed";
regulator-name = "+5V_USB_SS";
regulator-min-microvolt = <5000000>;
@ -1138,7 +1136,7 @@
vin-supply = <&vdd_5v0_sys>;
};
vdd_3v3_panel: regulator@8 {
vdd_3v3_panel: regulator-vdd-3v3-panel {
compatible = "regulator-fixed";
regulator-name = "+3.3V_PANEL";
regulator-min-microvolt = <3300000>;
@ -1148,7 +1146,7 @@
vin-supply = <&vdd_3v3_sys>;
};
vdd_hdmi_pll: regulator@9 {
vdd_hdmi_pll: regulator-vdd-hdmi-pll {
compatible = "regulator-fixed";
regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE";
regulator-min-microvolt = <1050000>;
@ -1157,7 +1155,7 @@
vin-supply = <&vdd_1v05_run>;
};
vdd_5v0_hdmi: regulator@10 {
vdd_5v0_hdmi: regulator-vdd-5v0-hdmi {
compatible = "regulator-fixed";
regulator-name = "+5V_HDMI_CON";
regulator-min-microvolt = <5000000>;
@ -1167,7 +1165,7 @@
vin-supply = <&vdd_5v0_sys>;
};
vdd_5v0_ts: regulator@11 {
vdd_5v0_ts: regulator-vdd-5v0-ts {
compatible = "regulator-fixed";
regulator-name = "+5V_VDD_TS";
regulator-min-microvolt = <5000000>;
@ -1178,7 +1176,7 @@
enable-active-high;
};
vdd_3v3_lp0: regulator@12 {
vdd_3v3_lp0: regulator-vdd-3v3-lp0 {
compatible = "regulator-fixed";
regulator-name = "+3.3V_LP0";
regulator-min-microvolt = <3300000>;

426
arch/arm64/boot/dts/nvidia/tegra132-peripherals-opp.dtsi Normal file
View File

@ -0,0 +1,426 @@
// SPDX-License-Identifier: GPL-2.0
/ {
/* EMC DVFS OPP table */
emc_icc_dvfs_opp_table: opp-table-dvfs0 {
compatible = "operating-points-v2";
opp-12750000-800 {
opp-microvolt = <800000 800000 1150000>;
opp-hz = /bits/ 64 <12750000>;
opp-supported-hw = <0x0003>;
};
opp-12750000-950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <12750000>;
opp-supported-hw = <0x0008>;
};
opp-12750000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <12750000>;
opp-supported-hw = <0x0010>;
};
opp-12750000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <12750000>;
opp-supported-hw = <0x0004>;
};
opp-20400000-800 {
opp-microvolt = <800000 800000 1150000>;
opp-hz = /bits/ 64 <20400000>;
opp-supported-hw = <0x0003>;
};
opp-20400000-950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <20400000>;
opp-supported-hw = <0x0008>;
};
opp-20400000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <20400000>;
opp-supported-hw = <0x0010>;
};
opp-20400000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <20400000>;
opp-supported-hw = <0x0004>;
};
opp-40800000-800 {
opp-microvolt = <800000 800000 1150000>;
opp-hz = /bits/ 64 <40800000>;
opp-supported-hw = <0x0003>;
};
opp-40800000-950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <40800000>;
opp-supported-hw = <0x0008>;
};
opp-40800000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <40800000>;
opp-supported-hw = <0x0010>;
};
opp-40800000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <40800000>;
opp-supported-hw = <0x0004>;
};
opp-68000000-800 {
opp-microvolt = <800000 800000 1150000>;
opp-hz = /bits/ 64 <68000000>;
opp-supported-hw = <0x0003>;
};
opp-68000000-950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <68000000>;
opp-supported-hw = <0x0008>;
};
opp-68000000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <68000000>;
opp-supported-hw = <0x0010>;
};
opp-68000000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <68000000>;
opp-supported-hw = <0x0004>;
};
opp-102000000-800 {
opp-microvolt = <800000 800000 1150000>;
opp-hz = /bits/ 64 <102000000>;
opp-supported-hw = <0x0003>;
};
opp-102000000-950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <102000000>;
opp-supported-hw = <0x0008>;
};
opp-102000000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <102000000>;
opp-supported-hw = <0x0010>;
};
opp-102000000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <102000000>;
opp-supported-hw = <0x0004>;
};
opp-204000000-800 {
opp-microvolt = <800000 800000 1150000>;
opp-hz = /bits/ 64 <204000000>;
opp-supported-hw = <0x0003>;
opp-suspend;
};
opp-204000000-950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <204000000>;
opp-supported-hw = <0x0008>;
opp-suspend;
};
opp-204000000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <204000000>;
opp-supported-hw = <0x0010>;
opp-suspend;
};
opp-204000000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <204000000>;
opp-supported-hw = <0x0004>;
opp-suspend;
};
opp-264000000-800 {
opp-microvolt = <800000 800000 1150000>;
opp-hz = /bits/ 64 <264000000>;
opp-supported-hw = <0x0003>;
};
opp-264000000-950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <264000000>;
opp-supported-hw = <0x0008>;
};
opp-264000000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <264000000>;
opp-supported-hw = <0x0010>;
};
opp-264000000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <264000000>;
opp-supported-hw = <0x0004>;
};
opp-300000000-850 {
opp-microvolt = <850000 850000 1150000>;
opp-hz = /bits/ 64 <300000000>;
opp-supported-hw = <0x0003>;
};
opp-300000000-950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <300000000>;
opp-supported-hw = <0x0008>;
};
opp-300000000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <300000000>;
opp-supported-hw = <0x0010>;
};
opp-300000000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <300000000>;
opp-supported-hw = <0x0004>;
};
opp-348000000-850 {
opp-microvolt = <850000 850000 1150000>;
opp-hz = /bits/ 64 <348000000>;
opp-supported-hw = <0x0003>;
};
opp-348000000-950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <348000000>;
opp-supported-hw = <0x0008>;
};
opp-348000000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <348000000>;
opp-supported-hw = <0x0010>;
};
opp-348000000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <348000000>;
opp-supported-hw = <0x0004>;
};
opp-396000000-950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <396000000>;
opp-supported-hw = <0x0008>;
};
opp-396000000-1000 {
opp-microvolt = <1000000 1000000 1150000>;
opp-hz = /bits/ 64 <396000000>;
opp-supported-hw = <0x0003>;
};
opp-396000000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <396000000>;
opp-supported-hw = <0x0010>;
};
opp-396000000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <396000000>;
opp-supported-hw = <0x0004>;
};
opp-528000000-950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <528000000>;
opp-supported-hw = <0x0008>;
};
opp-528000000-1000 {
opp-microvolt = <1000000 1000000 1150000>;
opp-hz = /bits/ 64 <528000000>;
opp-supported-hw = <0x0003>;
};
opp-528000000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <528000000>;
opp-supported-hw = <0x0010>;
};
opp-528000000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <528000000>;
opp-supported-hw = <0x0004>;
};
opp-600000000-950 {
opp-microvolt = <950000 950000 1150000>;
opp-hz = /bits/ 64 <600000000>;
opp-supported-hw = <0x0008>;
};
opp-600000000-1000 {
opp-microvolt = <1000000 1000000 1150000>;
opp-hz = /bits/ 64 <600000000>;
opp-supported-hw = <0x0003>;
};
opp-600000000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <600000000>;
opp-supported-hw = <0x0010>;
};
opp-600000000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <600000000>;
opp-supported-hw = <0x0004>;
};
opp-792000000-1000 {
opp-microvolt = <1000000 1000000 1150000>;
opp-hz = /bits/ 64 <792000000>;
opp-supported-hw = <0x000B>;
};
opp-792000000-1050 {
opp-microvolt = <1050000 1050000 1150000>;
opp-hz = /bits/ 64 <792000000>;
opp-supported-hw = <0x0010>;
};
opp-792000000-1110 {
opp-microvolt = <1110000 1110000 1150000>;
opp-hz = /bits/ 64 <792000000>;
opp-supported-hw = <0x0004>;
};
opp-924000000-1100 {
opp-microvolt = <1100000 1100000 1150000>;
opp-hz = /bits/ 64 <924000000>;
opp-supported-hw = <0x0013>;
};
opp-1200000000-1100 {
opp-microvolt = <1100000 1100000 1150000>;
opp-hz = /bits/ 64 <1200000000>;
opp-supported-hw = <0x0003>;
};
};
/* EMC bandwidth OPP table */
emc_bw_dfs_opp_table: opp-table-dvfs1 {
compatible = "operating-points-v2";
opp-12750000 {
opp-hz = /bits/ 64 <12750000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <204000>;
};
opp-20400000 {
opp-hz = /bits/ 64 <20400000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <326400>;
};
opp-40800000 {
opp-hz = /bits/ 64 <40800000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <652800>;
};
opp-68000000 {
opp-hz = /bits/ 64 <68000000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <1088000>;
};
opp-102000000 {
opp-hz = /bits/ 64 <102000000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <1632000>;
};
opp-204000000 {
opp-hz = /bits/ 64 <204000000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <3264000>;
opp-suspend;
};
opp-264000000 {
opp-hz = /bits/ 64 <264000000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <4224000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <4800000>;
};
opp-348000000 {
opp-hz = /bits/ 64 <348000000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <5568000>;
};
opp-396000000 {
opp-hz = /bits/ 64 <396000000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <6336000>;
};
opp-528000000 {
opp-hz = /bits/ 64 <528000000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <8448000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <9600000>;
};
opp-792000000 {
opp-hz = /bits/ 64 <792000000>;
opp-supported-hw = <0x001F>;
opp-peak-kBps = <12672000>;
};
opp-924000000 {
opp-hz = /bits/ 64 <924000000>;
opp-supported-hw = <0x0013>;
opp-peak-kBps = <14784000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-supported-hw = <0x0003>;
opp-peak-kBps = <19200000>;
};
};
};

48
arch/arm64/boot/dts/nvidia/tegra132.dtsi
View File

@ -8,6 +8,8 @@
#include <dt-bindings/thermal/tegra124-soctherm.h>
#include <dt-bindings/soc/tegra-pmc.h>
#include "tegra132-peripherals-opp.dtsi"
/ {
compatible = "nvidia,tegra132", "nvidia,tegra124";
interrupt-parent = <&lic>;
@ -210,7 +212,7 @@
};
timer@60005000 {
compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer";
reg = <0x0 0x60005000 0x0 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
@ -244,6 +246,10 @@
clock-names = "actmon", "emc";
resets = <&tegra_car 119>;
reset-names = "actmon";
operating-points-v2 = <&emc_bw_dfs_opp_table>;
interconnects = <&mc TEGRA124_MC_MPCORER &emc>;
interconnect-names = "cpu-read";
#cooling-cells = <2>;
};
gpio: gpio@6000d000 {
@ -394,7 +400,7 @@
};
i2c@7000c000 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra124-i2c";
reg = <0x0 0x7000c000 0x0 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -409,7 +415,7 @@
};
i2c@7000c400 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra124-i2c";
reg = <0x0 0x7000c400 0x0 0x100>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -424,7 +430,7 @@
};
i2c@7000c500 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra124-i2c";
reg = <0x0 0x7000c500 0x0 0x100>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -439,7 +445,7 @@
};
i2c@7000c700 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra124-i2c";
reg = <0x0 0x7000c700 0x0 0x100>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -454,7 +460,7 @@
};
i2c@7000d000 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra124-i2c";
reg = <0x0 0x7000d000 0x0 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -469,7 +475,7 @@
};
i2c@7000d100 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra124-i2c";
reg = <0x0 0x7000d100 0x0 0x100>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -607,15 +613,20 @@
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
#reset-cells = <1>;
#interconnect-cells = <1>;
};
emc: external-memory-controller@7001b000 {
compatible = "nvidia,tegra132-emc";
compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc";
reg = <0x0 0x7001b000 0x0 0x1000>;
clocks = <&tegra_car TEGRA124_CLK_EMC>;
clock-names = "emc";
nvidia,memory-controller = <&mc>;
operating-points-v2 = <&emc_icc_dvfs_opp_table>;
#interconnect-cells = <0>;
};
sata@70020000 {
@ -624,10 +635,8 @@
<0x0 0x70020000 0x0 0x7000>; /* SATA */
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_SATA>,
<&tegra_car TEGRA124_CLK_SATA_OOB>,
<&tegra_car TEGRA124_CLK_CML1>,
<&tegra_car TEGRA124_CLK_PLL_E>;
clock-names = "sata", "sata-oob", "cml1", "pll_e";
<&tegra_car TEGRA124_CLK_SATA_OOB>;
clock-names = "sata", "sata-oob";
resets = <&tegra_car 124>,
<&tegra_car 129>,
<&tegra_car 123>;
@ -665,8 +674,8 @@
<&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
<&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
<&tegra_car TEGRA124_CLK_XUSB_SS>,
<&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
<&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
<&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
<&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
<&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
<&tegra_car TEGRA124_CLK_PLL_U_480M>,
@ -674,7 +683,7 @@
<&tegra_car TEGRA124_CLK_PLL_E>;
clock-names = "xusb_host", "xusb_host_src",
"xusb_falcon_src", "xusb_ss",
"xusb_ss_src", "xusb_ss_div2",
"xusb_ss_div2", "xusb_ss_src",
"xusb_hs_src", "xusb_fs_src",
"pll_u_480m", "clk_m", "pll_e";
resets = <&tegra_car 89>, <&tegra_car 156>,
@ -886,7 +895,7 @@
};
thermal-zones {
cpu {
cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <0>;
@ -914,7 +923,8 @@
};
};
};
mem {
mem-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
@ -941,7 +951,8 @@
*/
};
};
gpu {
gpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <0>;
@ -969,7 +980,8 @@
};
};
};
pllx {
pllx-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;

20
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
View File

@ -1945,19 +1945,19 @@
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
input@0 {
reg = <0x0>;
label = "VDD_MUX";
shunt-resistor-micro-ohms = <20000>;
};
channel@1 {
input@1 {
reg = <0x1>;
label = "VDD_5V0_IO_SYS";
shunt-resistor-micro-ohms = <5000>;
};
channel@2 {
input@2 {
reg = <0x2>;
label = "VDD_3V3_SYS";
shunt-resistor-micro-ohms = <10000>;
@ -1970,19 +1970,19 @@
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
input@0 {
reg = <0x0>;
label = "VDD_3V3_IO_SLP";
shunt-resistor-micro-ohms = <10000>;
};
channel@1 {
input@1 {
reg = <0x1>;
label = "VDD_1V8_IO";
shunt-resistor-micro-ohms = <10000>;
};
channel@2 {
input@2 {
reg = <0x2>;
label = "VDD_M2_IN";
shunt-resistor-micro-ohms = <10000>;
@ -2250,7 +2250,7 @@
};
};
vdd_sd: regulator@100 {
vdd_sd: regulator-vdd-sd {
compatible = "regulator-fixed";
regulator-name = "SD_CARD_SW_PWR";
regulator-min-microvolt = <3300000>;
@ -2262,7 +2262,7 @@
vin-supply = <&vdd_3v3_sys>;
};
vdd_hdmi: regulator@101 {
vdd_hdmi: regulator-vdd-hdmi {
compatible = "regulator-fixed";
regulator-name = "VDD_HDMI_5V0";
regulator-min-microvolt = <5000000>;
@ -2274,7 +2274,7 @@
vin-supply = <&vdd_5v0_sys>;
};
vdd_usb0: regulator@102 {
vdd_usb0: regulator-vdd-usb0 {
compatible = "regulator-fixed";
regulator-name = "VDD_USB0";
regulator-min-microvolt = <5000000>;
@ -2286,7 +2286,7 @@
vin-supply = <&vdd_5v0_sys>;
};
vdd_usb1: regulator@103 {
vdd_usb1: regulator-vdd-usb1 {
compatible = "regulator-fixed";
regulator-name = "VDD_USB1";
regulator-min-microvolt = <5000000>;

20
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
View File

@ -44,7 +44,7 @@
#address-cells = <1>;
#size-cells = <0>;
phy: phy@0 {
phy: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
interrupt-parent = <&gpio>;
@ -73,19 +73,19 @@
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
input@0 {
reg = <0x0>;
label = "VDD_SYS_GPU";
shunt-resistor-micro-ohms = <10000>;
};
channel@1 {
input@1 {
reg = <0x1>;
label = "VDD_SYS_SOC";
shunt-resistor-micro-ohms = <10000>;
};
channel@2 {
input@2 {
reg = <0x2>;
label = "VDD_3V8_WIFI";
shunt-resistor-micro-ohms = <10000>;
@ -98,19 +98,19 @@
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
input@0 {
reg = <0x0>;
label = "VDD_IN";
shunt-resistor-micro-ohms = <5000>;
};
channel@1 {
input@1 {
reg = <0x1>;
label = "VDD_SYS_CPU";
shunt-resistor-micro-ohms = <10000>;
};
channel@2 {
input@2 {
reg = <0x2>;
label = "VDD_5V0_DDR";
shunt-resistor-micro-ohms = <10000>;
@ -393,7 +393,7 @@
method = "smc";
};
gnd: regulator@0 {
gnd: regulator-gnd {
compatible = "regulator-fixed";
regulator-name = "GND";
regulator-min-microvolt = <0>;
@ -402,7 +402,7 @@
regulator-boot-on;
};
vdd_5v0_sys: regulator@1 {
vdd_5v0_sys: regulator-vdd-5v0-sys {
compatible = "regulator-fixed";
regulator-name = "VDD_5V0_SYS";
regulator-min-microvolt = <5000000>;
@ -411,7 +411,7 @@
regulator-boot-on;
};
vdd_1v8_ap: regulator@2 {
vdd_1v8_ap: regulator-vdd-1v8-ap {
compatible = "regulator-fixed";
regulator-name = "VDD_1V8_AP";
regulator-min-microvolt = <1800000>;

50
arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts
View File

@ -46,7 +46,7 @@
#address-cells = <1>;
#size-cells = <0>;
phy: phy@0 {
phy: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
interrupt-parent = <&gpio_aon>;
@ -81,22 +81,22 @@
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
input@0 {
reg = <0>;
label = "VDD_IN";
shunt-resistor-micro-ohms = <5>;
};
channel@1 {
input@1 {
reg = <1>;
label = "VDD_CPU_GPU";
shunt-resistor-micro-ohms = <5>;
};
channel@2 {
input@2 {
reg = <2>;
label = "VDD_SOC";
shunt-resistor-micro-ohms = <>;
shunt-resistor-micro-ohms = <5>;
};
};
};
@ -593,7 +593,7 @@
method = "smc";
};
gnd: regulator@0 {
gnd: regulator-gnd {
compatible = "regulator-fixed";
regulator-name = "GND";
regulator-min-microvolt = <0>;
@ -602,7 +602,7 @@
regulator-boot-on;
};
vdd_5v0_sys: regulator@1 {
vdd_5v0_sys: regulator-vdd-5v0-sys {
compatible = "regulator-fixed";
regulator-name = "VDD_5V0_SYS";
regulator-min-microvolt = <5000000>;
@ -611,7 +611,7 @@
regulator-boot-on;
};
vdd_1v8_ap: regulator@2 {
vdd_1v8_ap: regulator-vdd-1v8-ap {
compatible = "regulator-fixed";
regulator-name = "VDD_1V8_AP";
regulator-min-microvolt = <1800000>;
@ -623,7 +623,7 @@
vin-supply = <&vdd_1v8>;
};
vdd_hdmi: regulator@3 {
vdd_hdmi: regulator-vdd-hdmi {
compatible = "regulator-fixed";
regulator-name = "VDD_5V0_HDMI_CON";
regulator-min-microvolt = <5000000>;
@ -633,7 +633,7 @@
};
thermal-zones {
cpu {
cpu-thermal {
polling-delay = <0>;
polling-delay-passive = <500>;
status = "okay";
@ -687,21 +687,7 @@
};
};
gpu {
polling-delay = <0>;
polling-delay-passive = <500>;
status = "okay";
trips {
gpu_alert0: critical {
temperature = <99000>;
hysteresis = <0>;
type = "critical";
};
};
};
aux {
aux-thermal {
polling-delay = <0>;
polling-delay-passive = <500>;
status = "okay";
@ -714,6 +700,20 @@
};
};
};
gpu-thermal {
polling-delay = <0>;
polling-delay-passive = <500>;
status = "okay";
trips {
gpu_alert0: critical {
temperature = <99000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
aconnect@2900000 {

95
arch/arm64/boot/dts/nvidia/tegra186.dtsi
View File

@ -508,6 +508,22 @@
};
};
timer@3010000 {
compatible = "nvidia,tegra186-timer";
reg = <0x0 0x03010000 0x0 0x000e0000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uarta: serial@3100000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x03100000 0x0 0x40>;
@ -569,7 +585,7 @@
};
gen1_i2c: i2c@3160000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x03160000 0x0 0x10000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -582,7 +598,7 @@
};
cam_i2c: i2c@3180000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x03180000 0x0 0x10000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -596,7 +612,7 @@
/* shares pads with dpaux1 */
dp_aux_ch1_i2c: i2c@3190000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x03190000 0x0 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -613,7 +629,7 @@
/* controlled by BPMP, should not be enabled */
pwr_i2c: i2c@31a0000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x031a0000 0x0 0x10000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -627,7 +643,7 @@
/* shares pads with dpaux0 */
dp_aux_ch0_i2c: i2c@31b0000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x031b0000 0x0 0x10000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -643,7 +659,7 @@
};
gen7_i2c: i2c@31c0000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x031c0000 0x0 0x10000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -656,7 +672,7 @@
};
gen9_i2c: i2c@31e0000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x031e0000 0x0 0x10000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -1073,7 +1089,7 @@
};
gen2_i2c: i2c@c240000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x0c240000 0x0 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -1086,7 +1102,7 @@
};
gen8_i2c: i2c@c250000 {
compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x0c250000 0x0 0x10000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -1199,7 +1215,7 @@
ccplex@e000000 {
compatible = "nvidia,tegra186-ccplex-cluster";
reg = <0x0 0x0e000000 0x0 0x3fffff>;
reg = <0x0 0x0e000000 0x0 0x400000>;
nvidia,bpmp = <&bpmp>;
};
@ -1538,6 +1554,21 @@
iommus = <&smmu TEGRA186_SID_VIC>;
};
nvjpg@15380000 {
compatible = "nvidia,tegra186-nvjpg";
reg = <0x15380000 0x40000>;
clocks = <&bpmp TEGRA186_CLK_NVJPG>;
clock-names = "nvjpg";
resets = <&bpmp TEGRA186_RESET_NVJPG>;
reset-names = "nvjpg";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_NVJPG>;
};
dsib: dsi@15400000 {
compatible = "nvidia,tegra186-dsi";
reg = <0x15400000 0x10000>;
@ -1569,6 +1600,21 @@
iommus = <&smmu TEGRA186_SID_NVDEC>;
};
nvenc@154c0000 {
compatible = "nvidia,tegra186-nvenc";
reg = <0x154c0000 0x40000>;
clocks = <&bpmp TEGRA186_CLK_NVENC>;
clock-names = "nvenc";
resets = <&bpmp TEGRA186_RESET_NVENC>;
reset-names = "nvenc";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_NVENC>;
};
sor0: sor@15540000 {
compatible = "nvidia,tegra186-sor";
reg = <0x15540000 0x10000>;
@ -1771,7 +1817,7 @@
iommus = <&smmu TEGRA186_SID_BPMP>;
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
TEGRA_HSP_DB_MASTER_BPMP>;
shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
@ -1930,12 +1976,12 @@
};
thermal-zones {
a57 {
/* Cortex-A57 cluster */
cpu-thermal {
polling-delay = <0>;
polling-delay-passive = <1000>;
thermal-sensors =
<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
trips {
critical {
@ -1949,12 +1995,12 @@
};
};
denver {
/* Denver cluster */
aux-thermal {
polling-delay = <0>;
polling-delay-passive = <1000>;
thermal-sensors =
<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
trips {
critical {
@ -1968,12 +2014,11 @@
};
};
gpu {
gpu-thermal {
polling-delay = <0>;
polling-delay-passive = <1000>;
thermal-sensors =
<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
trips {
critical {
@ -1987,12 +2032,11 @@
};
};
pll {
pll-thermal {
polling-delay = <0>;
polling-delay-passive = <1000>;
thermal-sensors =
<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
trips {
critical {
@ -2006,12 +2050,11 @@
};
};
always_on {
ao-thermal {
polling-delay = <0>;
polling-delay-passive = <1000>;
thermal-sensors =
<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
trips {
critical {

12
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
View File

@ -39,7 +39,7 @@
#address-cells = <1>;
#size-cells = <0>;
phy: phy@0 {
phy: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
interrupt-parent = <&gpio>;
@ -317,7 +317,7 @@
};
};
vdd_5v0_sys: regulator@0 {
vdd_5v0_sys: regulator-vdd-5v0-sys {
compatible = "regulator-fixed";
regulator-name = "VIN_SYS_5V0";
regulator-min-microvolt = <5000000>;
@ -326,7 +326,7 @@
regulator-boot-on;
};
vdd_hdmi: regulator@1 {
vdd_hdmi: regulator-vdd-hdmi {
compatible = "regulator-fixed";
regulator-name = "VDD_5V0_HDMI_CON";
regulator-min-microvolt = <5000000>;
@ -335,7 +335,7 @@
enable-active-high;
};
vdd_3v3_pcie: regulator@2 {
vdd_3v3_pcie: regulator-vdd-3v3-pcie {
compatible = "regulator-fixed";
regulator-name = "PEX_3V3";
regulator-min-microvolt = <3300000>;
@ -345,7 +345,7 @@
enable-active-high;
};
vdd_12v_pcie: regulator@3 {
vdd_12v_pcie: regulator-vdd-12v-pcie {
compatible = "regulator-fixed";
regulator-name = "VDD_12V";
regulator-min-microvolt = <1200000>;
@ -354,7 +354,7 @@
regulator-boot-on;
};
vdd_5v_sata: regulator@4 {
vdd_5v_sata: regulator-vdd-5v0-sata {
compatible = "regulator-fixed";
regulator-name = "VDD_5V_SATA";
regulator-min-microvolt = <5000000>;

8
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
View File

@ -1031,7 +1031,7 @@
i2s6_port: port@1 {
reg = <1>;
i2s6_dap_ep: endpoint@0 {
i2s6_dap_ep: endpoint {
dai-format = "i2s";
/* Place holder for external Codec */
};
@ -2097,7 +2097,7 @@
};
thermal-zones {
cpu {
cpu-thermal {
polling-delay = <0>;
polling-delay-passive = <500>;
status = "okay";
@ -2151,7 +2151,7 @@
};
};
gpu {
gpu-thermal {
polling-delay = <0>;
polling-delay-passive = <500>;
status = "okay";
@ -2165,7 +2165,7 @@
};
};
aux {
aux-thermal {
polling-delay = <0>;
polling-delay-passive = <500>;
status = "okay";

20
arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi
View File

@ -989,7 +989,7 @@
i2s5_port: port@1 {
reg = <1>;
i2s5_dap_ep: endpoint@0 {
i2s5_dap_ep: endpoint {
dai-format = "i2s";
/* Place holder for external Codec */
};
@ -1878,7 +1878,7 @@
status = "okay";
flash@0 {
compatible = "spi-nor";
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <102000000>;
spi-tx-bus-width = <4>;
@ -2000,7 +2000,7 @@
};
};
vdd_5v0_sys: regulator@100 {
vdd_5v0_sys: regulator-vdd-5v0-sys {
compatible = "regulator-fixed";
regulator-name = "VDD_5V_SYS";
regulator-min-microvolt = <5000000>;
@ -2009,7 +2009,7 @@
regulator-boot-on;
};
vdd_3v3_sys: regulator@101 {
vdd_3v3_sys: regulator-vdd-3v3-sys {
compatible = "regulator-fixed";
regulator-name = "VDD_3V3_SYS";
regulator-min-microvolt = <3300000>;
@ -2018,7 +2018,7 @@
regulator-boot-on;
};
vdd_3v3_ao: regulator@102 {
vdd_3v3_ao: regulator-vdd-3v3-ao {
compatible = "regulator-fixed";
regulator-name = "VDD_3V3_AO";
regulator-min-microvolt = <3300000>;
@ -2027,7 +2027,7 @@
regulator-boot-on;
};
vdd_1v8: regulator@103 {
vdd_1v8: regulator-vdd-1v8 {
compatible = "regulator-fixed";
regulator-name = "VDD_1V8";
regulator-min-microvolt = <1800000>;
@ -2036,7 +2036,7 @@
regulator-boot-on;
};
vdd_hdmi: regulator@104 {
vdd_hdmi: regulator-vdd-hdmi {
compatible = "regulator-fixed";
regulator-name = "VDD_5V0_HDMI_CON";
regulator-min-microvolt = <5000000>;
@ -2103,7 +2103,7 @@
};
thermal-zones {
cpu {
cpu-thermal {
polling-delay = <0>;
polling-delay-passive = <500>;
status = "okay";
@ -2157,7 +2157,7 @@
};
};
gpu {
gpu-thermal {
polling-delay = <0>;
polling-delay-passive = <500>;
status = "okay";
@ -2171,7 +2171,7 @@
};
};
aux {
aux-thermal {
polling-delay = <0>;
polling-delay-passive = <500>;
status = "okay";

2
arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi
View File

@ -20,7 +20,7 @@
};
};
vdd_3v3_sd: regulator@0 {
vdd_3v3_sd: regulator-vdd-3v3-sd {
compatible = "regulator-fixed";
regulator-name = "VDD_3V3_SD";
regulator-min-microvolt = <3300000>;

2
arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi
View File

@ -36,7 +36,7 @@
#address-cells = <1>;
#size-cells = <0>;
phy: phy@0 {
phy: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
interrupt-parent = <&gpio>;

231
arch/arm64/boot/dts/nvidia/tegra194.dtsi
View File

@ -3,6 +3,7 @@
#include <dt-bindings/gpio/tegra194-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/power/tegra194-powergate.h>
#include <dt-bindings/reset/tegra194-reset.h>
@ -535,7 +536,6 @@
pex_rst {
nvidia,pins = "pex_l5_rst_n_pgg1";
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@ -547,7 +547,6 @@
clkreq {
nvidia,pins = "pex_l5_clkreq_n_pgg0";
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@ -593,6 +592,7 @@
compatible = "nvidia,tegra194-emc";
reg = <0x0 0x02c60000 0x0 0x90000>,
<0x0 0x01780000 0x0 0x80000>;
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_EMC>;
clock-names = "emc";
@ -893,6 +893,9 @@
<&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA194_SID_SDMMC1>;
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc1_3v3>;
pinctrl-1 = <&sdmmc1_1v8>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout =
<0x07>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout =
@ -904,6 +907,10 @@
nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
nvidia,default-tap = <0x9>;
nvidia,default-trim = <0x5>;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-ddr50;
sd-uhs-sdr104;
status = "disabled";
};
@ -920,6 +927,9 @@
<&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA194_SID_SDMMC3>;
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc3_3v3>;
pinctrl-1 = <&sdmmc3_1v8>;
nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
@ -932,6 +942,10 @@
nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
nvidia,default-tap = <0x9>;
nvidia,default-trim = <0x5>;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-ddr50;
sd-uhs-sdr104;
status = "disabled";
};
@ -963,6 +977,11 @@
nvidia,default-tap = <0x8>;
nvidia,default-trim = <0x14>;
nvidia,dqs-trim = <40>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
supports-cqe;
status = "disabled";
};
@ -1182,7 +1201,7 @@
};
hsp_top0: hsp@3c00000 {
compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
compatible = "nvidia,tegra194-hsp";
reg = <0x03c00000 0xa0000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
@ -1360,7 +1379,7 @@
};
hsp_aon: hsp@c150000 {
compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
compatible = "nvidia,tegra194-hsp";
reg = <0x0c150000 0x90000>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
@ -1472,6 +1491,101 @@
#interrupt-cells = <2>;
interrupt-controller;
sdmmc1_3v3: sdmmc1-3v3 {
pins = "sdmmc1-hv";
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
};
sdmmc1_1v8: sdmmc1-1v8 {
pins = "sdmmc1-hv";
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
};
sdmmc3_3v3: sdmmc3-3v3 {
pins = "sdmmc3-hv";
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
};
sdmmc3_1v8: sdmmc3-1v8 {
pins = "sdmmc3-hv";
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
};
};
iommu@10000000 {
compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
reg = <0x10000000 0x800000>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
stream-match-mask = <0x7f80>;
#global-interrupts = <1>;
#iommu-cells = <1>;
nvidia,memory-controller = <&mc>;
status = "okay";
};
smmu: iommu@12000000 {
@ -1703,6 +1817,23 @@
<&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA194_SID_VIC>;
dma-coherent;
};
nvjpg@15380000 {
compatible = "nvidia,tegra194-nvjpg";
reg = <0x15380000 0x40000>;
clocks = <&bpmp TEGRA194_CLK_NVJPG>;
clock-names = "nvjpg";
resets = <&bpmp TEGRA194_RESET_NVJPG>;
reset-names = "nvjpg";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>,
<&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA194_SID_NVJPG>;
dma-coherent;
};
nvdec@15480000 {
@ -1724,6 +1855,25 @@
nvidia,host1x-class = <0xf0>;
};
nvenc@154c0000 {
compatible = "nvidia,tegra194-nvenc";
reg = <0x154c0000 0x40000>;
clocks = <&bpmp TEGRA194_CLK_NVENC>;
clock-names = "nvenc";
resets = <&bpmp TEGRA194_RESET_NVENC>;
reset-names = "nvenc";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>,
<&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>,
<&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>;
interconnect-names = "dma-mem", "read-1", "write";
iommus = <&smmu TEGRA194_SID_NVENC>;
dma-coherent;
nvidia,host1x-class = <0x21>;
};
dpaux0: dpaux@155c0000 {
compatible = "nvidia,tegra194-dpaux";
reg = <0x155c0000 0x10000>;
@ -1860,6 +2010,25 @@
};
};
nvenc@15a80000 {
compatible = "nvidia,tegra194-nvenc";
reg = <0x15a80000 0x00040000>;
clocks = <&bpmp TEGRA194_CLK_NVENC1>;
clock-names = "nvenc";
resets = <&bpmp TEGRA194_RESET_NVENC1>;
reset-names = "nvenc";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>,
<&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>,
<&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>;
interconnect-names = "dma-mem", "read-1", "write";
iommus = <&smmu TEGRA194_SID_NVENC1>;
dma-coherent;
nvidia,host1x-class = <0x22>;
};
sor0: sor@15b00000 {
compatible = "nvidia,tegra194-sor";
reg = <0x15b00000 0x40000>;
@ -2007,7 +2176,6 @@
#size-cells = <2>;
device_type = "pci";
num-lanes = <1>;
num-viewport = <8>;
linux,pci-domain = <1>;
clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
@ -2040,7 +2208,6 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA194_SID_PCIE1>;
iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>;
iommu-map-mask = <0x0>;
dma-coherent;
@ -2061,7 +2228,6 @@
#size-cells = <2>;
device_type = "pci";
num-lanes = <1>;
num-viewport = <8>;
linux,pci-domain = <2>;
clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
@ -2094,7 +2260,6 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA194_SID_PCIE2>;
iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>;
iommu-map-mask = <0x0>;
dma-coherent;
@ -2115,7 +2280,6 @@
#size-cells = <2>;
device_type = "pci";
num-lanes = <1>;
num-viewport = <8>;
linux,pci-domain = <3>;
clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
@ -2148,7 +2312,6 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA194_SID_PCIE3>;
iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>;
iommu-map-mask = <0x0>;
dma-coherent;
@ -2169,7 +2332,6 @@
#size-cells = <2>;
device_type = "pci";
num-lanes = <4>;
num-viewport = <8>;
linux,pci-domain = <4>;
clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
@ -2202,7 +2364,6 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA194_SID_PCIE4>;
iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
iommu-map-mask = <0x0>;
dma-coherent;
@ -2223,7 +2384,6 @@
#size-cells = <2>;
device_type = "pci";
num-lanes = <8>;
num-viewport = <8>;
linux,pci-domain = <0>;
clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
@ -2256,7 +2416,6 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA194_SID_PCIE0>;
iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
iommu-map-mask = <0x0>;
dma-coherent;
@ -2277,15 +2436,13 @@
#size-cells = <2>;
device_type = "pci";
num-lanes = <8>;
num-viewport = <8>;
linux,pci-domain = <5>;
pinctrl-names = "default";
pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>,
<&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
clock-names = "core", "core_m";
clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
clock-names = "core";
resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
<&bpmp TEGRA194_RESET_PEX1_CORE_5>;
@ -2314,7 +2471,6 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA194_SID_PCIE5>;
iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
iommu-map-mask = <0x0>;
dma-coherent;
@ -2354,7 +2510,6 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA194_SID_PCIE4>;
iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
iommu-map-mask = <0x0>;
dma-coherent;
@ -2394,7 +2549,6 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA194_SID_PCIE0>;
iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
iommu-map-mask = <0x0>;
dma-coherent;
@ -2437,7 +2591,6 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA194_SID_PCIE5>;
iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
iommu-map-mask = <0x0>;
dma-coherent;
@ -2467,7 +2620,7 @@
compatible = "nvidia,tegra186-bpmp";
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
TEGRA_HSP_DB_MASTER_BPMP>;
shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
@ -2731,7 +2884,7 @@
iommus = <&smmu TEGRA194_SID_APE>;
};
tcu: tcu {
tcu: serial {
compatible = "nvidia,tegra194-tcu";
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
<&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
@ -2739,39 +2892,33 @@
};
thermal-zones {
cpu {
thermal-sensors = <&{/bpmp/thermal}
TEGRA194_BPMP_THERMAL_ZONE_CPU>;
cpu-thermal {
thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>;
status = "disabled";
};
gpu {
thermal-sensors = <&{/bpmp/thermal}
TEGRA194_BPMP_THERMAL_ZONE_GPU>;
gpu-thermal {
thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>;
status = "disabled";
};
aux {
thermal-sensors = <&{/bpmp/thermal}
TEGRA194_BPMP_THERMAL_ZONE_AUX>;
aux-thermal {
thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>;
status = "disabled";
};
pllx {
thermal-sensors = <&{/bpmp/thermal}
TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
pllx-thermal {
thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
status = "disabled";
};
ao {
thermal-sensors = <&{/bpmp/thermal}
TEGRA194_BPMP_THERMAL_ZONE_AO>;
ao-thermal {
thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>;
status = "disabled";
};
tj {
thermal-sensors = <&{/bpmp/thermal}
TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
tj-thermal {
thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
status = "disabled";
};
};

4
arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
View File

@ -301,7 +301,7 @@
vqmmc-supply = <&vdd_1v8>;
};
clk32k_in: clock@0 {
clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
@ -336,7 +336,7 @@
method = "smc";
};
vdd_gpu: regulator@100 {
vdd_gpu: regulator-vdd-gpu {
compatible = "pwm-regulator";
pwms = <&pwm 1 8000>;
regulator-name = "VDD_GPU";

3
arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
View File

@ -11,11 +11,8 @@
pcie@1003000 {
status = "okay";
avdd-pll-uerefe-supply = <&avdd_1v05_pll>;
hvddio-pex-supply = <&vdd_1v8>;
dvddio-pex-supply = <&vdd_pex_1v05>;
dvdd-pex-pll-supply = <&vdd_pex_1v05>;
hvdd-pex-pll-e-supply = <&vdd_1v8>;
vddio-pex-ctl-supply = <&vdd_1v8>;
pci@1,0 {

2
arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi
View File

@ -40,7 +40,7 @@
non-removable;
};
clk32k_in: clock@0 {
clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;

37
arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
View File

@ -1361,11 +1361,6 @@
dvddio-pex-supply = <&vdd_pex_1v05>;
hvddio-pex-supply = <&vdd_1v8>;
avdd-usb-supply = <&vdd_3v3_sys>;
/* XXX what are these? */
avdd-pll-utmip-supply = <&vdd_1v8>;
avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>;
hvdd-usb-ss-pll-e-supply = <&vdd_1v8>;
status = "okay";
@ -1555,7 +1550,7 @@
};
};
vdd_sys_mux: regulator@0 {
vdd_sys_mux: regulator-vdd-sys-mux {
compatible = "regulator-fixed";
regulator-name = "VDD_SYS_MUX";
regulator-min-microvolt = <5000000>;
@ -1564,7 +1559,7 @@
regulator-boot-on;
};
vdd_5v0_sys: regulator@1 {
vdd_5v0_sys: regulator-vdd-5v0-sys {
compatible = "regulator-fixed";
regulator-name = "VDD_5V0_SYS";
regulator-min-microvolt = <5000000>;
@ -1576,7 +1571,7 @@
vin-supply = <&vdd_sys_mux>;
};
vdd_3v3_sys: regulator@2 {
vdd_3v3_sys: regulator-vdd-3v3-sys {
compatible = "regulator-fixed";
regulator-name = "VDD_3V3_SYS";
regulator-min-microvolt = <3300000>;
@ -1588,10 +1583,9 @@
vin-supply = <&vdd_sys_mux>;
regulator-enable-ramp-delay = <160>;
regulator-disable-ramp-delay = <10000>;
};
vdd_5v0_io: regulator@3 {
vdd_5v0_io: regulator-vdd-5v0-io {
compatible = "regulator-fixed";
regulator-name = "VDD_5V0_IO_SYS";
regulator-min-microvolt = <5000000>;
@ -1600,7 +1594,7 @@
regulator-boot-on;
};
vdd_3v3_sd: regulator@4 {
vdd_3v3_sd: regulator-vdd-3v3-sd {
compatible = "regulator-fixed";
regulator-name = "VDD_3V3_SD";
regulator-min-microvolt = <3300000>;
@ -1610,10 +1604,9 @@
vin-supply = <&vdd_3v3_sys>;
regulator-enable-ramp-delay = <472>;
regulator-disable-ramp-delay = <4880>;
};
vdd_dsi_csi: regulator@5 {
vdd_dsi_csi: regulator-vdd-dsi-csi {
compatible = "regulator-fixed";
regulator-name = "AVDD_DSI_CSI_1V2";
regulator-min-microvolt = <1200000>;
@ -1621,7 +1614,7 @@
vin-supply = <&vdd_sys_1v2>;
};
vdd_3v3_dis: regulator@6 {
vdd_3v3_dis: regulator-vdd-3v3-dis {
compatible = "regulator-fixed";
regulator-name = "VDD_DIS_3V3_LCD";
regulator-min-microvolt = <3300000>;
@ -1632,7 +1625,7 @@
vin-supply = <&vdd_3v3_sys>;
};
vdd_1v8_dis: regulator@7 {
vdd_1v8_dis: regulator-vdd-1v8-dis {
compatible = "regulator-fixed";
regulator-name = "VDD_LCD_1V8_DIS";
regulator-min-microvolt = <1800000>;
@ -1643,7 +1636,7 @@
vin-supply = <&vdd_1v8>;
};
vdd_5v0_rtl: regulator@8 {
vdd_5v0_rtl: regulator-vdd-5v0-rtl {
compatible = "regulator-fixed";
regulator-name = "RTL_5V";
regulator-min-microvolt = <5000000>;
@ -1653,7 +1646,7 @@
vin-supply = <&vdd_5v0_sys>;
};
vdd_usb_vbus: regulator@9 {
vdd_usb_vbus: regulator-vdd-usb-vbus {
compatible = "regulator-fixed";
regulator-name = "USB_VBUS_EN1";
regulator-min-microvolt = <5000000>;
@ -1663,7 +1656,7 @@
vin-supply = <&vdd_5v0_sys>;
};
vdd_hdmi: regulator@10 {
vdd_hdmi: regulator-vdd-hdmi {
compatible = "regulator-fixed";
regulator-name = "VDD_HDMI_5V0";
regulator-min-microvolt = <5000000>;
@ -1673,7 +1666,7 @@
vin-supply = <&vdd_5v0_sys>;
};
vdd_cam_1v2: regulator@11 {
vdd_cam_1v2: regulator-vdd-cam-1v8 {
compatible = "regulator-fixed";
regulator-name = "vdd-cam-1v2";
regulator-min-microvolt = <1200000>;
@ -1683,7 +1676,7 @@
vin-supply = <&vdd_3v3_sys>;
};
vdd_cam_2v8: regulator@12 {
vdd_cam_2v8: regulator-vdd-cam-2v8 {
compatible = "regulator-fixed";
regulator-name = "vdd-cam-2v8";
regulator-min-microvolt = <2800000>;
@ -1693,7 +1686,7 @@
vin-supply = <&vdd_3v3_sys>;
};
vdd_cam_1v8: regulator@13 {
vdd_cam_1v8: regulator-vdd-cam-1v8 {
compatible = "regulator-fixed";
regulator-name = "vdd-cam-1v8";
regulator-min-microvolt = <1800000>;
@ -1703,7 +1696,7 @@
vin-supply = <&vdd_3v3_sys>;
};
vdd_usb_vbus_otg: regulator@14 {
vdd_usb_vbus_otg: regulator-vdd-usb-vbus-otg {
compatible = "regulator-fixed";
regulator-name = "USB_VBUS_EN0";
regulator-min-microvolt = <5000000>;

40
arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi
View File

@ -1383,7 +1383,7 @@
};
};
gpio@0 {
hog-0 {
gpio-hog;
output-high;
gpios = <2 GPIO_ACTIVE_HIGH>,
@ -1586,7 +1586,7 @@
status = "okay";
};
clk32k_in: clock@0 {
clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
@ -1635,7 +1635,7 @@
method = "smc";
};
battery_reg: regulator@0 {
battery_reg: regulator-vdd-ac-bat {
compatible = "regulator-fixed";
regulator-name = "vdd-ac-bat";
regulator-min-microvolt = <5000000>;
@ -1643,7 +1643,7 @@
regulator-always-on;
};
vdd_3v3: regulator@1 {
vdd_3v3: regulator-vdd-3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd-3v3";
regulator-enable-ramp-delay = <160>;
@ -1655,7 +1655,7 @@
enable-active-high;
};
max77620_gpio7: regulator@2 {
max77620_gpio7: regulator-max77620-gpio7 {
compatible = "regulator-fixed";
regulator-name = "max77620-gpio7";
regulator-enable-ramp-delay = <240>;
@ -1669,7 +1669,7 @@
enable-active-high;
};
lcd_bl_en: regulator@3 {
lcd_bl_en: regulator-lcd-bl-en {
compatible = "regulator-fixed";
regulator-name = "lcd-bl-en";
regulator-min-microvolt = <1800000>;
@ -1680,7 +1680,7 @@
enable-active-high;
};
en_vdd_sd: regulator@4 {
en_vdd_sd: regulator-vdd-sd {
compatible = "regulator-fixed";
regulator-name = "en-vdd-sd";
regulator-enable-ramp-delay = <472>;
@ -1692,7 +1692,7 @@
enable-active-high;
};
en_vdd_cam: regulator@5 {
en_vdd_cam: regulator-vdd-cam {
compatible = "regulator-fixed";
regulator-name = "en-vdd-cam";
regulator-min-microvolt = <1800000>;
@ -1702,7 +1702,7 @@
enable-active-high;
};
vdd_sys_boost: regulator@6 {
vdd_sys_boost: regulator-vdd-sys-boost {
compatible = "regulator-fixed";
regulator-name = "vdd-sys-boost";
regulator-enable-ramp-delay = <3090>;
@ -1714,7 +1714,7 @@
enable-active-high;
};
vdd_hdmi: regulator@7 {
vdd_hdmi: regulator-vdd-hdmi {
compatible = "regulator-fixed";
regulator-name = "vdd-hdmi";
regulator-enable-ramp-delay = <468>;
@ -1727,21 +1727,21 @@
enable-active-high;
};
en_vdd_cpu_fixed: regulator@8 {
en_vdd_cpu_fixed: regulator-vdd-cpu-fixed {
compatible = "regulator-fixed";
regulator-name = "vdd-cpu-fixed";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
vdd_aux_3v3: regulator@9 {
vdd_aux_3v3: regulator-vdd-aux-3v3 {
compatible = "regulator-fixed";
regulator-name = "aux-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vdd_snsr_pm: regulator@10 {
vdd_snsr_pm: regulator-vdd-snsr-pm {
compatible = "regulator-fixed";
regulator-name = "snsr_pm";
regulator-min-microvolt = <3300000>;
@ -1750,7 +1750,7 @@
enable-active-high;
};
vdd_usb_5v0: regulator@11 {
vdd_usb_5v0: regulator-vdd-usb-5v0 {
compatible = "regulator-fixed";
status = "disabled";
regulator-name = "vdd-usb-5v0";
@ -1761,7 +1761,7 @@
enable-active-high;
};
vdd_cdc_1v2_aud: regulator@101 {
vdd_cdc_1v2_aud: regulator-vdd-cdc-1v2-aud {
compatible = "regulator-fixed";
status = "disabled";
regulator-name = "vdd_cdc_1v2_aud";
@ -1772,7 +1772,7 @@
enable-active-high;
};
vdd_disp_3v0: regulator@12 {
vdd_disp_3v0: regulator-vdd-disp-3v0 {
compatible = "regulator-fixed";
regulator-name = "vdd-disp-3v0";
regulator-enable-ramp-delay = <232>;
@ -1784,7 +1784,7 @@
enable-active-high;
};
vdd_fan: regulator@13 {
vdd_fan: regulator-vdd-fan {
compatible = "regulator-fixed";
regulator-name = "vdd-fan";
regulator-enable-ramp-delay = <284>;
@ -1795,7 +1795,7 @@
enable-active-high;
};
usb_vbus1: regulator@14 {
usb_vbus1: regulator-usb-vbus1 {
compatible = "regulator-fixed";
regulator-name = "usb-vbus1";
regulator-min-microvolt = <5000000>;
@ -1806,7 +1806,7 @@
gpio-open-drain;
};
usb_vbus2: regulator@15 {
usb_vbus2: regulator-usb-vbus2 {
compatible = "regulator-fixed";
regulator-name = "usb-vbus2";
regulator-min-microvolt = <5000000>;
@ -1817,7 +1817,7 @@
gpio-open-drain;
};
vdd_3v3_eth: regulator@16 {
vdd_3v3_eth: regulator-vdd-3v3-eth {
compatible = "regulator-fixed";
regulator-name = "vdd-3v3-eth-a02";
regulator-min-microvolt = <3300000>;

53
arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
View File

@ -30,11 +30,8 @@
pcie@1003000 {
status = "okay";
avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
hvddio-pex-supply = <&vdd_1v8>;
dvddio-pex-supply = <&vdd_pex_1v05>;
dvdd-pex-pll-supply = <&vdd_pex_1v05>;
hvdd-pex-pll-e-supply = <&vdd_1v8>;
vddio-pex-ctl-supply = <&vdd_1v8>;
pci@1,0 {
@ -266,7 +263,6 @@
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1170000>;
regulator-enable-ramp-delay = <146>;
regulator-disable-ramp-delay = <4080>;
regulator-ramp-delay = <27500>;
regulator-ramp-delay-scale = <300>;
regulator-always-on;
@ -282,7 +278,6 @@
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
regulator-enable-ramp-delay = <176>;
regulator-disable-ramp-delay = <145800>;
regulator-ramp-delay = <27500>;
regulator-ramp-delay-scale = <300>;
regulator-always-on;
@ -298,7 +293,6 @@
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-enable-ramp-delay = <176>;
regulator-disable-ramp-delay = <32000>;
regulator-ramp-delay = <27500>;
regulator-ramp-delay-scale = <350>;
regulator-always-on;
@ -314,7 +308,6 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <242>;
regulator-disable-ramp-delay = <118000>;
regulator-ramp-delay = <27500>;
regulator-ramp-delay-scale = <360>;
regulator-always-on;
@ -330,7 +323,6 @@
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-enable-ramp-delay = <26>;
regulator-disable-ramp-delay = <626>;
regulator-ramp-delay = <100000>;
regulator-ramp-delay-scale = <200>;
regulator-always-on;
@ -346,7 +338,6 @@
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
regulator-enable-ramp-delay = <22>;
regulator-disable-ramp-delay = <650>;
regulator-ramp-delay = <100000>;
regulator-ramp-delay-scale = <200>;
@ -360,7 +351,6 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <62>;
regulator-disable-ramp-delay = <650>;
regulator-ramp-delay = <100000>;
regulator-ramp-delay-scale = <200>;
@ -378,7 +368,6 @@
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1100000>;
regulator-enable-ramp-delay = <22>;
regulator-disable-ramp-delay = <610>;
regulator-ramp-delay = <100000>;
regulator-ramp-delay-scale = <200>;
regulator-disable-active-discharge;
@ -403,7 +392,6 @@
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
regulator-enable-ramp-delay = <24>;
regulator-disable-ramp-delay = <2768>;
regulator-ramp-delay = <100000>;
regulator-ramp-delay-scale = <200>;
@ -417,7 +405,6 @@
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
regulator-enable-ramp-delay = <22>;
regulator-disable-ramp-delay = <1160>;
regulator-ramp-delay = <100000>;
regulator-ramp-delay-scale = <200>;
@ -456,11 +443,6 @@
avdd-usb-supply = <&vdd_3v3_sys>;
dvddio-pex-supply = <&vdd_pex_1v05>;
hvddio-pex-supply = <&vdd_1v8>;
/* these really belong to the XUSB pad controller */
avdd-pll-utmip-supply = <&vdd_1v8>;
avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>;
hvdd-usb-ss-pll-e-supply = <&vdd_1v8>;
status = "okay";
};
@ -688,7 +670,7 @@
i2s4_port: port@1 {
reg = <1>;
i2s4_dap_ep: endpoint@0 {
i2s4_dap_ep: endpoint {
dai-format = "i2s";
/* Placeholder for external Codec */
};
@ -706,7 +688,7 @@
port@0 {
reg = <0>;
dmic1_cif_ep: endpoint@0 {
dmic1_cif_ep: endpoint {
remote-endpoint = <&xbar_dmic1_ep>;
};
};
@ -714,7 +696,7 @@
dmic1_port: port@1 {
reg = <1>;
dmic1_dap_ep: endpoint@0 {
dmic1_dap_ep: endpoint {
/* Placeholder for external Codec */
};
};
@ -731,7 +713,7 @@
port@0 {
reg = <0>;
dmic2_cif_ep: endpoint@0 {
dmic2_cif_ep: endpoint {
remote-endpoint = <&xbar_dmic2_ep>;
};
};
@ -739,7 +721,7 @@
dmic2_port: port@1 {
reg = <1>;
dmic2_dap_ep: endpoint@0 {
dmic2_dap_ep: endpoint {
/* Placeholder for external Codec */
};
};
@ -1637,7 +1619,7 @@
status = "okay";
flash@0 {
compatible = "spi-nor";
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <104000000>;
spi-tx-bus-width = <2>;
@ -1645,7 +1627,7 @@
};
};
clk32k_in: clock@0 {
clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
@ -1684,7 +1666,7 @@
};
thermal-zones {
cpu {
cpu-thermal {
trips {
cpu_trip_critical: critical {
temperature = <96500>;
@ -1762,7 +1744,7 @@
method = "smc";
};
vdd_5v0_sys: regulator@0 {
vdd_5v0_sys: regulator-vdd-5v0-sys {
compatible = "regulator-fixed";
regulator-name = "VDD_5V0_SYS";
@ -1772,14 +1754,13 @@
regulator-boot-on;
};
vdd_3v3_sys: regulator@1 {
vdd_3v3_sys: regulator-vdd-3v3-sys {
compatible = "regulator-fixed";
regulator-name = "VDD_3V3_SYS";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <240>;
regulator-disable-ramp-delay = <11340>;
regulator-always-on;
regulator-boot-on;
@ -1789,7 +1770,7 @@
vin-supply = <&vdd_5v0_sys>;
};
vdd_3v3_sd: regulator@2 {
vdd_3v3_sd: regulator-vdd-3v3-sd {
compatible = "regulator-fixed";
regulator-name = "VDD_3V3_SD";
@ -1802,7 +1783,7 @@
vin-supply = <&vdd_3v3_sys>;
};
vdd_hdmi: regulator@3 {
vdd_hdmi: regulator-vdd-hdmi-5v0 {
compatible = "regulator-fixed";
regulator-name = "VDD_HDMI_5V0";
@ -1812,7 +1793,7 @@
vin-supply = <&vdd_5v0_sys>;
};
vdd_hub_3v3: regulator@4 {
vdd_hub_3v3: regulator-vdd-hub-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDD_HUB_3V3";
@ -1825,7 +1806,7 @@
vin-supply = <&vdd_5v0_sys>;
};
vdd_cpu: regulator@5 {
vdd_cpu: regulator-vdd-cpu {
compatible = "regulator-fixed";
regulator-name = "VDD_CPU";
@ -1840,7 +1821,7 @@
vin-supply = <&vdd_5v0_sys>;
};
vdd_gpu: regulator@6 {
vdd_gpu: regulator-vdd-gpu {
compatible = "pwm-regulator";
pwms = <&pwm 1 8000>;
@ -1855,7 +1836,7 @@
vin-supply = <&vdd_5v0_sys>;
};
avdd_io_edp_1v05: regulator@7 {
avdd_io_edp_1v05: regulator-avdd-io-epd-1v05 {
compatible = "regulator-fixed";
regulator-name = "AVDD_IO_EDP_1V05";
@ -1868,7 +1849,7 @@
vin-supply = <&avdd_1v05_pll>;
};
vdd_5v0_usb: regulator@8 {
vdd_5v0_usb: regulator-vdd-5v-usb {
compatible = "regulator-fixed";
regulator-name = "VDD_5V_USB";

22
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
View File

@ -1642,10 +1642,6 @@
dvddio-pex-supply = <&avddio_1v05>;
hvddio-pex-supply = <&pp1800>;
avdd-usb-supply = <&pp3300>;
avdd-pll-utmip-supply = <&pp1800>;
avdd-pll-uerefe-supply = <&pp1050_avdd>;
dvdd-pex-pll-supply = <&avddio_1v05>;
hvdd-pex-pll-e-supply = <&pp1800>;
status = "okay";
};
@ -1726,7 +1722,7 @@
};
};
clk32k_in: clock@0 {
clk32k_in: clock-32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
@ -1807,7 +1803,7 @@
method = "smc";
};
ppvar_sys: regulator@0 {
ppvar_sys: regulator-ppvar-sys {
compatible = "regulator-fixed";
regulator-name = "PPVAR_SYS";
regulator-min-microvolt = <4400000>;
@ -1815,7 +1811,7 @@
regulator-always-on;
};
pplcd_vdd: regulator@1 {
pplcd_vdd: regulator-pplcd-vdd {
compatible = "regulator-fixed";
regulator-name = "PPLCD_VDD";
regulator-min-microvolt = <4400000>;
@ -1825,7 +1821,7 @@
regulator-boot-on;
};
pp3000_always: regulator@2 {
pp3000_always: regulator-pp3000-always {
compatible = "regulator-fixed";
regulator-name = "PP3000_ALWAYS";
regulator-min-microvolt = <3000000>;
@ -1833,7 +1829,7 @@
regulator-always-on;
};
pp3300: regulator@3 {
pp3300: regulator-pp3000 {
compatible = "regulator-fixed";
regulator-name = "PP3300";
regulator-min-microvolt = <3300000>;
@ -1843,7 +1839,7 @@
enable-active-high;
};
pp5000: regulator@4 {
pp5000: regulator-pp5000 {
compatible = "regulator-fixed";
regulator-name = "PP5000";
regulator-min-microvolt = <5000000>;
@ -1851,7 +1847,7 @@
regulator-always-on;
};
pp1800_lcdio: regulator@5 {
pp1800_lcdio: regulator-pp1800-lcdio {
compatible = "regulator-fixed";
regulator-name = "PP1800_LCDIO";
regulator-min-microvolt = <1800000>;
@ -1861,7 +1857,7 @@
regulator-boot-on;
};
pp1800_cam: regulator@6 {
pp1800_cam: regulator-pp1800-cam {
compatible = "regulator-fixed";
regulator-name = "PP1800_CAM";
regulator-min-microvolt = <1800000>;
@ -1870,7 +1866,7 @@
enable-active-high;
};
usbc_vbus: regulator@7 {
usbc_vbus: regulator-usbc-vbus {
compatible = "regulator-fixed";
regulator-name = "USBC_VBUS";
regulator-min-microvolt = <5000000>;

27
arch/arm64/boot/dts/nvidia/tegra210.dtsi
View File

@ -93,8 +93,8 @@
interrupt-names = "syncpt", "host1x";
clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
clock-names = "host1x";
resets = <&tegra_car 28>;
reset-names = "host1x";
resets = <&tegra_car 28>, <&mc TEGRA210_MC_RESET_HC>;
reset-names = "host1x", "mc";
#address-cells = <2>;
#size-cells = <2>;
@ -181,6 +181,12 @@
tsec@54100000 {
compatible = "nvidia,tegra210-tsec";
reg = <0x0 0x54100000 0x0 0x00040000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_TSEC>;
clock-names = "tsec";
resets = <&tegra_car 83>;
reset-names = "tsec";
status = "disabled";
};
dc@54200000 {
@ -283,6 +289,11 @@
tsec@54500000 {
compatible = "nvidia,tegra210-tsec";
reg = <0x0 0x54500000 0x0 0x00040000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_TSECB>;
clock-names = "tsec";
resets = <&tegra_car 206>;
reset-names = "tsec";
status = "disabled";
};
@ -1015,8 +1026,8 @@
<&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
<&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
<&tegra_car TEGRA210_CLK_XUSB_SS>,
<&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
<&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
<&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
<&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
<&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
<&tegra_car TEGRA210_CLK_PLL_U_480M>,
@ -1024,7 +1035,7 @@
<&tegra_car TEGRA210_CLK_PLL_E>;
clock-names = "xusb_host", "xusb_host_src",
"xusb_falcon_src", "xusb_ss",
"xusb_ss_src", "xusb_ss_div2",
"xusb_ss_div2", "xusb_ss_src",
"xusb_hs_src", "xusb_fs_src",
"pll_u_480m", "clk_m", "pll_e";
resets = <&tegra_car 89>, <&tegra_car 156>,
@ -1981,7 +1992,7 @@
};
thermal-zones {
cpu {
cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <0>;
@ -2010,7 +2021,7 @@
};
};
mem {
mem-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
@ -2056,7 +2067,7 @@
};
};
gpu {
gpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <0>;
@ -2085,7 +2096,7 @@
};
};
pllx {
pllx-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;

24
arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi Normal file
View File

@ -0,0 +1,24 @@
// SPDX-License-Identifier: GPL-2.0
#include "tegra234.dtsi"
/ {
model = "NVIDIA Jetson AGX Orin";
compatible = "nvidia,p3701-0000", "nvidia,tegra234";
bus@0 {
mmc@3460000 {
status = "okay";
bus-width = <8>;
non-removable;
};
rtc@c2a0000 {
status = "okay";
};
pmc@c360000 {
nvidia,invert-interrupt;
};
};
};

24
arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts Normal file
View File

@ -0,0 +1,24 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra234-p3701-0000.dtsi"
#include "tegra234-p3737-0000.dtsi"
/ {
model = "NVIDIA Jetson AGX Orin Developer Kit";
compatible = "nvidia,p3737-0000+p3701-0000", "nvidia,p3701-0000", "nvidia,tegra234";
aliases {
mmc3 = "/bus@0/mmc@3460000";
serial0 = &tcu;
};
chosen {
bootargs = "console=ttyS0,115200n8";
stdout-path = "serial0:115200n8";
};
serial {
status = "okay";
};
};

5
arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi Normal file
View File

@ -0,0 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
/ {
compatible = "nvidia,p3737-0000";
};

1
arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts
View File

@ -26,7 +26,6 @@
status = "okay";
bus-width = <8>;
non-removable;
only-1-8-v;
};
rtc@c2a0000 {

541
arch/arm64/boot/dts/nvidia/tegra234.dtsi
View File

@ -3,6 +3,7 @@
#include <dt-bindings/clock/tegra234-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
#include <dt-bindings/memory/tegra234-mc.h>
#include <dt-bindings/reset/tegra234-reset.h>
/ {
@ -25,6 +26,113 @@
status = "okay";
};
gpio: gpio@2200000 {
compatible = "nvidia,tegra234-gpio";
reg-names = "security", "gpio";
reg = <0x02200000 0x10000>,
<0x02210000 0x10000>;
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
#gpio-cells = <2>;
gpio-controller;
};
mc: memory-controller@2c00000 {
compatible = "nvidia,tegra234-mc";
reg = <0x02c00000 0x100000>,
<0x02b80000 0x040000>,
<0x01700000 0x100000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
#interconnect-cells = <1>;
status = "okay";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
<0x02b80000 0x0 0x02b80000 0x0 0x040000>,
<0x02c00000 0x0 0x02c00000 0x0 0x100000>;
/*
* Bit 39 of addresses passing through the memory
* controller selects the XBAR format used when memory
* is accessed. This is used to transparently access
* memory in the XBAR format used by the discrete GPU
* (bit 39 set) or Tegra (bit 39 clear).
*
* As a consequence, the operating system must ensure
* that bit 39 is never used implicitly, for example
* via an I/O virtual address mapping of an IOMMU. If
* devices require access to the XBAR switch, their
* drivers must set this bit explicitly.
*
* Limit the DMA range for memory clients to [38:0].
*/
dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
emc: external-memory-controller@2c60000 {
compatible = "nvidia,tegra234-emc";
reg = <0x0 0x02c60000 0x0 0x90000>,
<0x0 0x01780000 0x0 0x80000>;
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA234_CLK_EMC>;
clock-names = "emc";
status = "okay";
#interconnect-cells = <0>;
nvidia,bpmp = <&bpmp>;
};
};
uarta: serial@3100000 {
compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
reg = <0x03100000 0x10000>;
@ -40,11 +148,27 @@
compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
reg = <0x03460000 0x20000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA234_CLK_SDMMC4>;
clock-names = "sdhci";
clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
<&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
clock-names = "sdhci", "tmclk";
assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
<&bpmp TEGRA234_CLK_PLLC4>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>;
resets = <&bpmp TEGRA234_RESET_SDMMC4>;
reset-names = "sdhci";
dma-coherent;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>,
<&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>;
interconnect-names = "dma-mem", "write";
nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
nvidia,default-tap = <0x8>;
nvidia,default-trim = <0x14>;
nvidia,dqs-trim = <40>;
supports-cqe;
status = "disabled";
};
@ -93,9 +217,26 @@
reg = <0x0c2a0000 0x10000>;
interrupt-parent = <&pmc>;
interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA234_CLK_CLK_32K>;
clock-names = "rtc";
status = "disabled";
};
gpio_aon: gpio@c2f0000 {
compatible = "nvidia,tegra234-gpio-aon";
reg-names = "security", "gpio";
reg = <0x0c2f0000 0x1000>,
<0x0c2f1000 0x1000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
#gpio-cells = <2>;
gpio-controller;
};
pmc: pmc@c360000 {
compatible = "nvidia,tegra234-pmc";
reg = <0x0c360000 0x10000>,
@ -122,21 +263,21 @@
};
};
sysram@40000000 {
sram@40000000 {
compatible = "nvidia,tegra234-sysram", "mmio-sram";
reg = <0x0 0x40000000 0x0 0x50000>;
reg = <0x0 0x40000000 0x0 0x80000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x40000000 0x50000>;
ranges = <0x0 0x0 0x40000000 0x80000>;
cpu_bpmp_tx: shmem@4e000 {
reg = <0x4e000 0x1000>;
cpu_bpmp_tx: sram@70000 {
reg = <0x70000 0x1000>;
label = "cpu-bpmp-tx";
pool;
};
cpu_bpmp_rx: shmem@4f000 {
reg = <0x4f000 0x1000>;
cpu_bpmp_rx: sram@71000 {
reg = <0x71000 0x1000>;
label = "cpu-bpmp-rx";
pool;
};
@ -146,10 +287,15 @@
compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
TEGRA_HSP_DB_MASTER_BPMP>;
shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>,
<&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>;
interconnect-names = "read", "write", "dma-mem", "dma-write";
bpmp_i2c: i2c {
compatible = "nvidia,tegra186-bpmp-i2c";
@ -163,12 +309,373 @@
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
cpu0_0: cpu@0 {
compatible = "arm,cortex-a78";
device_type = "cpu";
reg = <0x000>;
reg = <0x00000>;
enable-method = "psci";
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c0_0>;
};
cpu0_1: cpu@100 {
compatible = "arm,cortex-a78";
device_type = "cpu";
reg = <0x00100>;
enable-method = "psci";
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c0_1>;
};
cpu0_2: cpu@200 {
compatible = "arm,cortex-a78";
device_type = "cpu";
reg = <0x00200>;
enable-method = "psci";
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c0_2>;
};
cpu0_3: cpu@300 {
compatible = "arm,cortex-a78";
device_type = "cpu";
reg = <0x00300>;
enable-method = "psci";
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c0_3>;
};
cpu1_0: cpu@10000 {
compatible = "arm,cortex-a78";
device_type = "cpu";
reg = <0x10000>;
enable-method = "psci";
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c1_0>;
};
cpu1_1: cpu@10100 {
compatible = "arm,cortex-a78";
device_type = "cpu";
reg = <0x10100>;
enable-method = "psci";
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c1_1>;
};
cpu1_2: cpu@10200 {
compatible = "arm,cortex-a78";
device_type = "cpu";
reg = <0x10200>;
enable-method = "psci";
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c1_2>;
};
cpu1_3: cpu@10300 {
compatible = "arm,cortex-a78";
device_type = "cpu";
reg = <0x10300>;
enable-method = "psci";
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c1_3>;
};
cpu2_0: cpu@20000 {
compatible = "arm,cortex-a78";
device_type = "cpu";
reg = <0x20000>;
enable-method = "psci";
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c2_0>;
};
cpu2_1: cpu@20100 {
compatible = "arm,cortex-a78";
device_type = "cpu";
reg = <0x20100>;
enable-method = "psci";
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c2_1>;
};
cpu2_2: cpu@20200 {
compatible = "arm,cortex-a78";
device_type = "cpu";
reg = <0x20200>;
enable-method = "psci";
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c2_2>;
};
cpu2_3: cpu@20300 {
compatible = "arm,cortex-a78";
device_type = "cpu";
reg = <0x20300>;
enable-method = "psci";
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c2_3>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0_0>;
};
core1 {
cpu = <&cpu0_1>;
};
core2 {
cpu = <&cpu0_2>;
};
core3 {
cpu = <&cpu0_3>;
};
};
cluster1 {
core0 {
cpu = <&cpu1_0>;
};
core1 {
cpu = <&cpu1_1>;
};
core2 {
cpu = <&cpu1_2>;
};
core3 {
cpu = <&cpu1_3>;
};
};
cluster2 {
core0 {
cpu = <&cpu2_0>;
};
core1 {
cpu = <&cpu2_1>;
};
core2 {
cpu = <&cpu2_2>;
};
core3 {
cpu = <&cpu2_3>;
};
};
};
l2c0_0: l2-cache00 {
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
next-level-cache = <&l3c0>;
};
l2c0_1: l2-cache01 {
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
next-level-cache = <&l3c0>;
};
l2c0_2: l2-cache02 {
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
next-level-cache = <&l3c0>;
};
l2c0_3: l2-cache03 {
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
next-level-cache = <&l3c0>;
};
l2c1_0: l2-cache10 {
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
next-level-cache = <&l3c1>;
};
l2c1_1: l2-cache11 {
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
next-level-cache = <&l3c1>;
};
l2c1_2: l2-cache12 {
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
next-level-cache = <&l3c1>;
};
l2c1_3: l2-cache13 {
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
next-level-cache = <&l3c1>;
};
l2c2_0: l2-cache20 {
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
next-level-cache = <&l3c2>;
};
l2c2_1: l2-cache21 {
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
next-level-cache = <&l3c2>;
};
l2c2_2: l2-cache22 {
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
next-level-cache = <&l3c2>;
};
l2c2_3: l2-cache23 {
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
next-level-cache = <&l3c2>;
};
l3c0: l3-cache0 {
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
};
l3c1: l3-cache1 {
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
};
l3c2: l3-cache2 {
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
};
};
pmu {
compatible = "arm,cortex-a78-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
psci {
@ -177,6 +684,14 @@
method = "smc";
};
tcu: serial {
compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu";
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
<&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
mbox-names = "rx", "tx";
status = "disabled";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,