DaVinci SoC updates for v5.6 include migrating DM365 SoC to use
drivers/clocksource based driver for timer. This leads to removal of machine specific timer driver. There are two patches adding missing fixed regulators for audio codecs on DM365 and DM644x EVMs. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJeHgPjAAoJEGFBu2jqvgRN8NkP/Rf6HDaFX/LAq8NQNz0PanFW Dgd3pWtyY2w+TyXJZX9aUsYwU6xyTB79C9z6mOPo31H1oNRkKK+DeaDC2NSGj1Nt CtFKefaPATUzFUO/xB4GK8LHint9gPI+wolo7QTxXDhZTssf6/lUCkcgMUC5gzCj 0ilIZvNt4Ud0Nz3C46GyqDUqlBwnI/WAkGc5HLahzTi4eYz0WX/5Beu5ffbG1pnc ID0hfxQA28PDJ/1abs9EOLJvpezPK8gyUuSe16b99PIeoL4sP9PurBM40RAd9pxq h/ljHsSt8+VmPbqTQd393vybASebOx4JiLnPMKXCFupwz1PJ+R8D83TkG9FMPwxX 8XwUvayB72n2oJKiC1BgVGywX4cwqhJCskoKAgCM0t0OuAuqFilMBFQCvDL9yg1C 11M+umd6xtsqK1b9E5qTXMK3wWZ5y/XstsW3Uwdc0S2a53MIy4uXIuDK8tyL/i84 x2nnW/ZAtMmikPtCtM0EXuvVJ6PU4ayMYba7uzVBT6Xe4aKXudsjj68inC+Jnqh4 qHtSHq1IW5P1Ru5k1jPgJNjSuv57G41zcqmx4tOwwEjEyw7XGwUA00aAmoD5enTs lz2O25l3A102POmKaFEfzPL4P2p4JDlHA8cP/vvNLB1BxnXdqIGzrRiJqF2RkItM hJoKADfRHL5AoP7F8rx/ =02go -----END PGP SIGNATURE----- Merge tag 'davinci-for-v5.6/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into arm/late DaVinci SoC updates for v5.6 include migrating DM365 SoC to use drivers/clocksource based driver for timer. This leads to removal of machine specific timer driver. There are two patches adding missing fixed regulators for audio codecs on DM365 and DM644x EVMs. * tag 'davinci-for-v5.6/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: ARM: davinci: dm644x-evm: Add Fixed regulators needed for tlv320aic33 ARM: davinci: dm365-evm: Add Fixed regulators needed for tlv320aic3101 ARM: davinci: remove legacy timer support ARM: davinci: dm365: switch to using the clocksource driver clocksource: davinci: only enable clockevents once tim34 is initialized Link: https://lore.kernel.org/r/043eb5b2-a302-4de6-a3e8-8238e49483b1@ti.com/ Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
a832eb203e
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@ -7,8 +7,7 @@
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ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
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# Common objects
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obj-y := time.o serial.o usb.o \
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common.o sram.o
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obj-y := serial.o usb.o common.o sram.o
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obj-$(CONFIG_DAVINCI_MUX) += mux.o
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|
|
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@ -30,6 +30,8 @@
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#include <linux/spi/eeprom.h>
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#include <linux/v4l2-dv-timings.h>
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#include <linux/platform_data/ti-aemif.h>
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#include <linux/regulator/fixed.h>
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#include <linux/regulator/machine.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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@ -245,6 +247,19 @@ static struct davinci_i2c_platform_data i2c_pdata = {
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.bus_delay = 0 /* usec */,
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};
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/* Fixed regulator support */
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static struct regulator_consumer_supply fixed_supplies_3_3v[] = {
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/* Baseboard 3.3V: 5V -> TPS767D301 -> 3.3V */
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REGULATOR_SUPPLY("AVDD", "1-0018"),
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REGULATOR_SUPPLY("DRVDD", "1-0018"),
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REGULATOR_SUPPLY("IOVDD", "1-0018"),
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};
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static struct regulator_consumer_supply fixed_supplies_1_8v[] = {
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/* Baseboard 1.8V: 5V -> TPS767D301 -> 1.8V */
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REGULATOR_SUPPLY("DVDD", "1-0018"),
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};
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static int dm365evm_keyscan_enable(struct device *dev)
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{
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return davinci_cfg_reg(DM365_KEYSCAN);
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@ -800,6 +815,11 @@ static __init void dm365_evm_init(void)
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if (ret)
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pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
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regulator_register_always_on(0, "fixed-dummy", fixed_supplies_1_8v,
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ARRAY_SIZE(fixed_supplies_1_8v), 1800000);
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regulator_register_always_on(1, "fixed-dummy", fixed_supplies_3_3v,
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ARRAY_SIZE(fixed_supplies_3_3v), 3300000);
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nvmem_add_cell_table(&davinci_nvmem_cell_table);
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nvmem_add_cell_lookups(&davinci_nvmem_cell_lookup, 1);
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@ -29,6 +29,8 @@
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#include <linux/v4l2-dv-timings.h>
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#include <linux/export.h>
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#include <linux/leds.h>
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#include <linux/regulator/fixed.h>
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#include <linux/regulator/machine.h>
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#include <media/i2c/tvp514x.h>
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@ -653,6 +655,19 @@ static struct i2c_board_info __initdata i2c_info[] = {
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},
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};
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/* Fixed regulator support */
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static struct regulator_consumer_supply fixed_supplies_3_3v[] = {
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/* Baseboard 3.3V: 5V -> TPS54310PWP -> 3.3V */
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REGULATOR_SUPPLY("AVDD", "1-001b"),
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REGULATOR_SUPPLY("DRVDD", "1-001b"),
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};
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static struct regulator_consumer_supply fixed_supplies_1_8v[] = {
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/* Baseboard 1.8V: 5V -> TPS54310PWP -> 1.8V */
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REGULATOR_SUPPLY("IOVDD", "1-001b"),
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REGULATOR_SUPPLY("DVDD", "1-001b"),
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};
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#define DM644X_I2C_SDA_PIN GPIO_TO_PIN(2, 12)
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#define DM644X_I2C_SCL_PIN GPIO_TO_PIN(2, 11)
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@ -831,6 +846,11 @@ static __init void davinci_evm_init(void)
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dm644x_register_clocks();
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regulator_register_always_on(0, "fixed-dummy", fixed_supplies_1_8v,
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ARRAY_SIZE(fixed_supplies_1_8v), 1800000);
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regulator_register_always_on(1, "fixed-dummy", fixed_supplies_3_3v,
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ARRAY_SIZE(fixed_supplies_3_3v), 3300000);
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dm644x_init_devices();
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ret = dm644x_gpio_register();
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|
|
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|
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@ -21,7 +21,6 @@
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#include <mach/common.h>
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#include <mach/cputype.h>
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#include <mach/da8xx.h>
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#include <mach/time.h>
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#include "asp.h"
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#include "cpuidle.h"
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|
|
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|
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@ -17,7 +17,6 @@
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#include <mach/hardware.h>
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#include <mach/cputype.h>
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#include <mach/mux.h>
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#include <mach/time.h>
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#include "davinci.h"
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#include "irqs.h"
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|
@ -303,21 +302,3 @@ int davinci_gpio_register(struct resource *res, int size, void *pdata)
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davinci_gpio_device.dev.platform_data = pdata;
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return platform_device_register(&davinci_gpio_device);
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}
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/*-------------------------------------------------------------------------*/
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/*-------------------------------------------------------------------------*/
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struct davinci_timer_instance davinci_timer_instance[2] = {
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{
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.base = DAVINCI_TIMER0_BASE,
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.bottom_irq = DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12),
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.top_irq = DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34),
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},
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{
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.base = DAVINCI_TIMER1_BASE,
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.bottom_irq = DAVINCI_INTC_IRQ(IRQ_TINT1_TINT12),
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.top_irq = DAVINCI_INTC_IRQ(IRQ_TINT1_TINT34),
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},
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};
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|
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@ -35,7 +35,8 @@
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#include <mach/cputype.h>
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#include <mach/mux.h>
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#include <mach/serial.h>
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#include <mach/time.h>
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#include <clocksource/timer-davinci.h>
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#include "asp.h"
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#include "davinci.h"
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@ -660,10 +661,16 @@ static struct davinci_id dm365_ids[] = {
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},
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};
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static struct davinci_timer_info dm365_timer_info = {
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.timers = davinci_timer_instance,
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.clockevent_id = T0_BOT,
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.clocksource_id = T0_TOP,
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/*
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* Bottom half of timer0 is used for clockevent, top half is used for
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* clocksource.
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*/
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static const struct davinci_timer_cfg dm365_timer_cfg = {
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.reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_128),
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.irq = {
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DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
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DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
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},
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};
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#define DM365_UART1_BASE (IO_PHYS + 0x106000)
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@ -723,7 +730,6 @@ static const struct davinci_soc_info davinci_soc_info_dm365 = {
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.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
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.pinmux_pins = dm365_pins,
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.pinmux_pins_num = ARRAY_SIZE(dm365_pins),
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.timer_info = &dm365_timer_info,
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.emac_pdata = &dm365_emac_pdata,
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.sram_dma = 0x00010000,
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.sram_len = SZ_32K,
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@ -771,6 +777,7 @@ void __init dm365_init_time(void)
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{
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void __iomem *pll1, *pll2, *psc;
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struct clk *clk;
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int rv;
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clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM365_REF_FREQ);
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@ -789,7 +796,8 @@ void __init dm365_init_time(void)
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return;
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}
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davinci_timer_init(clk);
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rv = davinci_timer_register(clk, &dm365_timer_cfg);
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WARN(rv, "Unable to register the timer: %d\n", rv);
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}
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void __init dm365_register_clocks(void)
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|
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@ -22,22 +22,6 @@
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#define DAVINCI_INTC_START NR_IRQS
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#define DAVINCI_INTC_IRQ(_irqnum) (DAVINCI_INTC_START + (_irqnum))
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void davinci_timer_init(struct clk *clk);
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struct davinci_timer_instance {
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u32 base;
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u32 bottom_irq;
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u32 top_irq;
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unsigned long cmp_off;
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unsigned int cmp_irq;
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};
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struct davinci_timer_info {
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struct davinci_timer_instance *timers;
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unsigned int clockevent_id;
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unsigned int clocksource_id;
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};
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struct davinci_gpio_controller;
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/*
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@ -58,7 +42,6 @@ struct davinci_soc_info {
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u32 pinmux_base;
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const struct mux_config *pinmux_pins;
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unsigned long pinmux_pins_num;
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struct davinci_timer_info *timer_info;
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int gpio_type;
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u32 gpio_base;
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unsigned gpio_num;
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|
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@ -1,33 +0,0 @@
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/*
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* Local header file for DaVinci time code.
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*
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* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
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*
|
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* 2007 (c) MontaVista Software, Inc. This file is licensed under
|
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* the terms of the GNU General Public License version 2. This program
|
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* is licensed "as is" without any warranty of any kind, whether express
|
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* or implied.
|
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*/
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#ifndef __ARCH_ARM_MACH_DAVINCI_TIME_H
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#define __ARCH_ARM_MACH_DAVINCI_TIME_H
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#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800)
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|
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enum {
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T0_BOT,
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T0_TOP,
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T1_BOT,
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T1_TOP,
|
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NUM_TIMERS
|
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};
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#define IS_TIMER1(id) (id & 0x2)
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#define IS_TIMER0(id) (!IS_TIMER1(id))
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#define IS_TIMER_TOP(id) ((id & 0x1))
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#define IS_TIMER_BOT(id) (!IS_TIMER_TOP(id))
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#define ID_TO_TIMER(id) (IS_TIMER1(id) != 0)
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extern struct davinci_timer_instance davinci_timer_instance[];
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|
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#endif /* __ARCH_ARM_MACH_DAVINCI_TIME_H */
|
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|
|
@ -1,400 +0,0 @@
|
|||
/*
|
||||
* DaVinci timer subsystem
|
||||
*
|
||||
* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
|
||||
*
|
||||
* 2007 (c) MontaVista Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/clockchips.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/sched_clock.h>
|
||||
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
#include <mach/cputype.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/time.h>
|
||||
|
||||
static struct clock_event_device clockevent_davinci;
|
||||
static unsigned int davinci_clock_tick_rate;
|
||||
|
||||
/*
|
||||
* This driver configures the 2 64-bit count-up timers as 4 independent
|
||||
* 32-bit count-up timers used as follows:
|
||||
*/
|
||||
|
||||
enum {
|
||||
TID_CLOCKEVENT,
|
||||
TID_CLOCKSOURCE,
|
||||
};
|
||||
|
||||
/* Timer register offsets */
|
||||
#define PID12 0x0
|
||||
#define TIM12 0x10
|
||||
#define TIM34 0x14
|
||||
#define PRD12 0x18
|
||||
#define PRD34 0x1c
|
||||
#define TCR 0x20
|
||||
#define TGCR 0x24
|
||||
#define WDTCR 0x28
|
||||
|
||||
/* Offsets of the 8 compare registers */
|
||||
#define CMP12_0 0x60
|
||||
#define CMP12_1 0x64
|
||||
#define CMP12_2 0x68
|
||||
#define CMP12_3 0x6c
|
||||
#define CMP12_4 0x70
|
||||
#define CMP12_5 0x74
|
||||
#define CMP12_6 0x78
|
||||
#define CMP12_7 0x7c
|
||||
|
||||
/* Timer register bitfields */
|
||||
#define TCR_ENAMODE_DISABLE 0x0
|
||||
#define TCR_ENAMODE_ONESHOT 0x1
|
||||
#define TCR_ENAMODE_PERIODIC 0x2
|
||||
#define TCR_ENAMODE_MASK 0x3
|
||||
|
||||
#define TGCR_TIMMODE_SHIFT 2
|
||||
#define TGCR_TIMMODE_64BIT_GP 0x0
|
||||
#define TGCR_TIMMODE_32BIT_UNCHAINED 0x1
|
||||
#define TGCR_TIMMODE_64BIT_WDOG 0x2
|
||||
#define TGCR_TIMMODE_32BIT_CHAINED 0x3
|
||||
|
||||
#define TGCR_TIM12RS_SHIFT 0
|
||||
#define TGCR_TIM34RS_SHIFT 1
|
||||
#define TGCR_RESET 0x0
|
||||
#define TGCR_UNRESET 0x1
|
||||
#define TGCR_RESET_MASK 0x3
|
||||
|
||||
struct timer_s {
|
||||
char *name;
|
||||
unsigned int id;
|
||||
unsigned long period;
|
||||
unsigned long opts;
|
||||
unsigned long flags;
|
||||
void __iomem *base;
|
||||
unsigned long tim_off;
|
||||
unsigned long prd_off;
|
||||
unsigned long enamode_shift;
|
||||
struct irqaction irqaction;
|
||||
};
|
||||
static struct timer_s timers[];
|
||||
|
||||
/* values for 'opts' field of struct timer_s */
|
||||
#define TIMER_OPTS_DISABLED 0x01
|
||||
#define TIMER_OPTS_ONESHOT 0x02
|
||||
#define TIMER_OPTS_PERIODIC 0x04
|
||||
#define TIMER_OPTS_STATE_MASK 0x07
|
||||
|
||||
#define TIMER_OPTS_USE_COMPARE 0x80000000
|
||||
#define USING_COMPARE(t) ((t)->opts & TIMER_OPTS_USE_COMPARE)
|
||||
|
||||
static char *id_to_name[] = {
|
||||
[T0_BOT] = "timer0_0",
|
||||
[T0_TOP] = "timer0_1",
|
||||
[T1_BOT] = "timer1_0",
|
||||
[T1_TOP] = "timer1_1",
|
||||
};
|
||||
|
||||
static int timer32_config(struct timer_s *t)
|
||||
{
|
||||
u32 tcr;
|
||||
struct davinci_soc_info *soc_info = &davinci_soc_info;
|
||||
|
||||
if (USING_COMPARE(t)) {
|
||||
struct davinci_timer_instance *dtip =
|
||||
soc_info->timer_info->timers;
|
||||
int event_timer = ID_TO_TIMER(timers[TID_CLOCKEVENT].id);
|
||||
|
||||
/*
|
||||
* Next interrupt should be the current time reg value plus
|
||||
* the new period (using 32-bit unsigned addition/wrapping
|
||||
* to 0 on overflow). This assumes that the clocksource
|
||||
* is setup to count to 2^32-1 before wrapping around to 0.
|
||||
*/
|
||||
__raw_writel(__raw_readl(t->base + t->tim_off) + t->period,
|
||||
t->base + dtip[event_timer].cmp_off);
|
||||
} else {
|
||||
tcr = __raw_readl(t->base + TCR);
|
||||
|
||||
/* disable timer */
|
||||
tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift);
|
||||
__raw_writel(tcr, t->base + TCR);
|
||||
|
||||
/* reset counter to zero, set new period */
|
||||
__raw_writel(0, t->base + t->tim_off);
|
||||
__raw_writel(t->period, t->base + t->prd_off);
|
||||
|
||||
/* Set enable mode */
|
||||
if (t->opts & TIMER_OPTS_ONESHOT)
|
||||
tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift;
|
||||
else if (t->opts & TIMER_OPTS_PERIODIC)
|
||||
tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift;
|
||||
|
||||
__raw_writel(tcr, t->base + TCR);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline u32 timer32_read(struct timer_s *t)
|
||||
{
|
||||
return __raw_readl(t->base + t->tim_off);
|
||||
}
|
||||
|
||||
static irqreturn_t timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct clock_event_device *evt = &clockevent_davinci;
|
||||
|
||||
evt->event_handler(evt);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/* called when 32-bit counter wraps */
|
||||
static irqreturn_t freerun_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct timer_s timers[] = {
|
||||
[TID_CLOCKEVENT] = {
|
||||
.name = "clockevent",
|
||||
.opts = TIMER_OPTS_DISABLED,
|
||||
.irqaction = {
|
||||
.flags = IRQF_TIMER,
|
||||
.handler = timer_interrupt,
|
||||
}
|
||||
},
|
||||
[TID_CLOCKSOURCE] = {
|
||||
.name = "free-run counter",
|
||||
.period = ~0,
|
||||
.opts = TIMER_OPTS_PERIODIC,
|
||||
.irqaction = {
|
||||
.flags = IRQF_TIMER,
|
||||
.handler = freerun_interrupt,
|
||||
}
|
||||
},
|
||||
};
|
||||
|
||||
static void __init timer_init(void)
|
||||
{
|
||||
struct davinci_soc_info *soc_info = &davinci_soc_info;
|
||||
struct davinci_timer_instance *dtip = soc_info->timer_info->timers;
|
||||
void __iomem *base[2];
|
||||
int i;
|
||||
|
||||
/* Global init of each 64-bit timer as a whole */
|
||||
for(i=0; i<2; i++) {
|
||||
u32 tgcr;
|
||||
|
||||
base[i] = ioremap(dtip[i].base, SZ_4K);
|
||||
if (WARN_ON(!base[i]))
|
||||
continue;
|
||||
|
||||
/* Disabled, Internal clock source */
|
||||
__raw_writel(0, base[i] + TCR);
|
||||
|
||||
/* reset both timers, no pre-scaler for timer34 */
|
||||
tgcr = 0;
|
||||
__raw_writel(tgcr, base[i] + TGCR);
|
||||
|
||||
/* Set both timers to unchained 32-bit */
|
||||
tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
|
||||
__raw_writel(tgcr, base[i] + TGCR);
|
||||
|
||||
/* Unreset timers */
|
||||
tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
|
||||
(TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
|
||||
__raw_writel(tgcr, base[i] + TGCR);
|
||||
|
||||
/* Init both counters to zero */
|
||||
__raw_writel(0, base[i] + TIM12);
|
||||
__raw_writel(0, base[i] + TIM34);
|
||||
}
|
||||
|
||||
/* Init of each timer as a 32-bit timer */
|
||||
for (i=0; i< ARRAY_SIZE(timers); i++) {
|
||||
struct timer_s *t = &timers[i];
|
||||
int timer = ID_TO_TIMER(t->id);
|
||||
u32 irq;
|
||||
|
||||
t->base = base[timer];
|
||||
if (!t->base)
|
||||
continue;
|
||||
|
||||
if (IS_TIMER_BOT(t->id)) {
|
||||
t->enamode_shift = 6;
|
||||
t->tim_off = TIM12;
|
||||
t->prd_off = PRD12;
|
||||
irq = dtip[timer].bottom_irq;
|
||||
} else {
|
||||
t->enamode_shift = 22;
|
||||
t->tim_off = TIM34;
|
||||
t->prd_off = PRD34;
|
||||
irq = dtip[timer].top_irq;
|
||||
}
|
||||
|
||||
/* Register interrupt */
|
||||
t->irqaction.name = t->name;
|
||||
t->irqaction.dev_id = (void *)t;
|
||||
|
||||
if (t->irqaction.handler != NULL) {
|
||||
irq = USING_COMPARE(t) ? dtip[i].cmp_irq : irq;
|
||||
setup_irq(irq, &t->irqaction);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* clocksource
|
||||
*/
|
||||
static u64 read_cycles(struct clocksource *cs)
|
||||
{
|
||||
struct timer_s *t = &timers[TID_CLOCKSOURCE];
|
||||
|
||||
return (cycles_t)timer32_read(t);
|
||||
}
|
||||
|
||||
static struct clocksource clocksource_davinci = {
|
||||
.rating = 300,
|
||||
.read = read_cycles,
|
||||
.mask = CLOCKSOURCE_MASK(32),
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
||||
/*
|
||||
* Overwrite weak default sched_clock with something more precise
|
||||
*/
|
||||
static u64 notrace davinci_read_sched_clock(void)
|
||||
{
|
||||
return timer32_read(&timers[TID_CLOCKSOURCE]);
|
||||
}
|
||||
|
||||
/*
|
||||
* clockevent
|
||||
*/
|
||||
static int davinci_set_next_event(unsigned long cycles,
|
||||
struct clock_event_device *evt)
|
||||
{
|
||||
struct timer_s *t = &timers[TID_CLOCKEVENT];
|
||||
|
||||
t->period = cycles;
|
||||
timer32_config(t);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int davinci_shutdown(struct clock_event_device *evt)
|
||||
{
|
||||
struct timer_s *t = &timers[TID_CLOCKEVENT];
|
||||
|
||||
t->opts &= ~TIMER_OPTS_STATE_MASK;
|
||||
t->opts |= TIMER_OPTS_DISABLED;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int davinci_set_oneshot(struct clock_event_device *evt)
|
||||
{
|
||||
struct timer_s *t = &timers[TID_CLOCKEVENT];
|
||||
|
||||
t->opts &= ~TIMER_OPTS_STATE_MASK;
|
||||
t->opts |= TIMER_OPTS_ONESHOT;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int davinci_set_periodic(struct clock_event_device *evt)
|
||||
{
|
||||
struct timer_s *t = &timers[TID_CLOCKEVENT];
|
||||
|
||||
t->period = davinci_clock_tick_rate / (HZ);
|
||||
t->opts &= ~TIMER_OPTS_STATE_MASK;
|
||||
t->opts |= TIMER_OPTS_PERIODIC;
|
||||
timer32_config(t);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct clock_event_device clockevent_davinci = {
|
||||
.features = CLOCK_EVT_FEAT_PERIODIC |
|
||||
CLOCK_EVT_FEAT_ONESHOT,
|
||||
.set_next_event = davinci_set_next_event,
|
||||
.set_state_shutdown = davinci_shutdown,
|
||||
.set_state_periodic = davinci_set_periodic,
|
||||
.set_state_oneshot = davinci_set_oneshot,
|
||||
};
|
||||
|
||||
void __init davinci_timer_init(struct clk *timer_clk)
|
||||
{
|
||||
struct davinci_soc_info *soc_info = &davinci_soc_info;
|
||||
unsigned int clockevent_id;
|
||||
unsigned int clocksource_id;
|
||||
int i;
|
||||
|
||||
clockevent_id = soc_info->timer_info->clockevent_id;
|
||||
clocksource_id = soc_info->timer_info->clocksource_id;
|
||||
|
||||
timers[TID_CLOCKEVENT].id = clockevent_id;
|
||||
timers[TID_CLOCKSOURCE].id = clocksource_id;
|
||||
|
||||
/*
|
||||
* If using same timer for both clock events & clocksource,
|
||||
* a compare register must be used to generate an event interrupt.
|
||||
* This is equivalent to a oneshot timer only (not periodic).
|
||||
*/
|
||||
if (clockevent_id == clocksource_id) {
|
||||
struct davinci_timer_instance *dtip =
|
||||
soc_info->timer_info->timers;
|
||||
int event_timer = ID_TO_TIMER(clockevent_id);
|
||||
|
||||
/* Only bottom timers can use compare regs */
|
||||
if (IS_TIMER_TOP(clockevent_id))
|
||||
pr_warn("%s: Invalid use of system timers. Results unpredictable.\n",
|
||||
__func__);
|
||||
else if ((dtip[event_timer].cmp_off == 0)
|
||||
|| (dtip[event_timer].cmp_irq == 0))
|
||||
pr_warn("%s: Invalid timer instance setup. Results unpredictable.\n",
|
||||
__func__);
|
||||
else {
|
||||
timers[TID_CLOCKEVENT].opts |= TIMER_OPTS_USE_COMPARE;
|
||||
clockevent_davinci.features = CLOCK_EVT_FEAT_ONESHOT;
|
||||
}
|
||||
}
|
||||
|
||||
BUG_ON(IS_ERR(timer_clk));
|
||||
clk_prepare_enable(timer_clk);
|
||||
|
||||
/* init timer hw */
|
||||
timer_init();
|
||||
|
||||
davinci_clock_tick_rate = clk_get_rate(timer_clk);
|
||||
|
||||
/* setup clocksource */
|
||||
clocksource_davinci.name = id_to_name[clocksource_id];
|
||||
if (clocksource_register_hz(&clocksource_davinci,
|
||||
davinci_clock_tick_rate))
|
||||
pr_err("%s: can't register clocksource!\n",
|
||||
clocksource_davinci.name);
|
||||
|
||||
sched_clock_register(davinci_read_sched_clock, 32,
|
||||
davinci_clock_tick_rate);
|
||||
|
||||
/* setup clockevent */
|
||||
clockevent_davinci.name = id_to_name[timers[TID_CLOCKEVENT].id];
|
||||
|
||||
clockevent_davinci.cpumask = cpumask_of(0);
|
||||
clockevents_config_and_register(&clockevent_davinci,
|
||||
davinci_clock_tick_rate, 1, 0xfffffffe);
|
||||
|
||||
for (i=0; i< ARRAY_SIZE(timers); i++)
|
||||
timer32_config(&timers[i]);
|
||||
}
|
||||
|
|
@ -302,10 +302,6 @@ int __init davinci_timer_register(struct clk *clk,
|
|||
return rv;
|
||||
}
|
||||
|
||||
clockevents_config_and_register(&clockevent->dev, tick_rate,
|
||||
DAVINCI_TIMER_MIN_DELTA,
|
||||
DAVINCI_TIMER_MAX_DELTA);
|
||||
|
||||
davinci_clocksource.dev.rating = 300;
|
||||
davinci_clocksource.dev.read = davinci_clocksource_read;
|
||||
davinci_clocksource.dev.mask =
|
||||
|
|
@ -323,6 +319,10 @@ int __init davinci_timer_register(struct clk *clk,
|
|||
davinci_clocksource_init_tim34(base);
|
||||
}
|
||||
|
||||
clockevents_config_and_register(&clockevent->dev, tick_rate,
|
||||
DAVINCI_TIMER_MIN_DELTA,
|
||||
DAVINCI_TIMER_MAX_DELTA);
|
||||
|
||||
rv = clocksource_register_hz(&davinci_clocksource.dev, tick_rate);
|
||||
if (rv) {
|
||||
pr_err("Unable to register clocksource");
|
||||
|
|
|
|||
Loading…
Reference in New Issue