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arm64: dts: mt8183: Add node for the Mali GPU 

Add a basic GPU node for mt8183, as well as OPP table.

Note that with the current panfrost driver, devfreq is not
actually functional, as the we do not have platform-specific
support for >1 supplies. Also, we are missing code to handle
frequency change, as the GPU frequency needs to be switched
away to a stable 26Mhz clock during the transition.

Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Link: https://lore.kernel.org/r/20210521200038.v14.1.I9f45f5c1f975422d58b5904d11546349e9ccdc94@changeid
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Nicolas Boichat 2021-05-21 20:00:41 +08:00 committed by Matthias Brugger
parent 507b1b2812
commit a8168cebf1
4 changed files with 120 additions and 0 deletions
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5
arch/arm64/boot/dts/mediatek/mt8183-evb.dts
View File

@ -42,6 +42,11 @@
status = "okay";
};
&gpu {
mali-supply = <&mt6358_vgpu_reg>;
sram-supply = <&mt6358_vsram_gpu_reg>;
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins_0>;

5
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
View File

@ -279,6 +279,11 @@
};
};
&gpu {
mali-supply = <&mt6358_vgpu_reg>;
sram-supply = <&mt6358_vsram_gpu_reg>;
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;

5
arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
View File

@ -68,6 +68,11 @@
status = "okay";
};
&gpu {
mali-supply = <&mt6358_vgpu_reg>;
sram-supply = <&mt6358_vsram_gpu_reg>;
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins_0>;

105
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View File

@ -197,6 +197,91 @@
};
};
gpu_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <625000>, <850000>;
};
opp-320000000 {
opp-hz = /bits/ 64 <320000000>;
opp-microvolt = <631250>, <850000>;
};
opp-340000000 {
opp-hz = /bits/ 64 <340000000>;
opp-microvolt = <637500>, <850000>;
};
opp-360000000 {
opp-hz = /bits/ 64 <360000000>;
opp-microvolt = <643750>, <850000>;
};
opp-380000000 {
opp-hz = /bits/ 64 <380000000>;
opp-microvolt = <650000>, <850000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <656250>, <850000>;
};
opp-420000000 {
opp-hz = /bits/ 64 <420000000>;
opp-microvolt = <662500>, <850000>;
};
opp-460000000 {
opp-hz = /bits/ 64 <460000000>;
opp-microvolt = <675000>, <850000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <687500>, <850000>;
};
opp-540000000 {
opp-hz = /bits/ 64 <540000000>;
opp-microvolt = <700000>, <850000>;
};
opp-580000000 {
opp-hz = /bits/ 64 <580000000>;
opp-microvolt = <712500>, <850000>;
};
opp-620000000 {
opp-hz = /bits/ 64 <620000000>;
opp-microvolt = <725000>, <850000>;
};
opp-653000000 {
opp-hz = /bits/ 64 <653000000>;
opp-microvolt = <743750>, <850000>;
};
opp-698000000 {
opp-hz = /bits/ 64 <698000000>;
opp-microvolt = <768750>, <868750>;
};
opp-743000000 {
opp-hz = /bits/ 64 <743000000>;
opp-microvolt = <793750>, <893750>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <825000>, <925000>;
};
};
pmu-a53 {
compatible = "arm,cortex-a53-pmu";
interrupt-parent = <&gic>;
@ -1118,6 +1203,26 @@
#clock-cells = <1>;
};
gpu: gpu@13040000 {
compatible = "mediatek,mt8183-mali", "arm,mali-bifrost";
reg = <0 0x13040000 0 0x4000>;
interrupts =
<GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "job", "mmu", "gpu";
clocks = <&topckgen CLK_TOP_MFGPLL_CK>;
power-domains =
<&spm MT8183_POWER_DOMAIN_MFG_CORE0>,
<&spm MT8183_POWER_DOMAIN_MFG_CORE1>,
<&spm MT8183_POWER_DOMAIN_MFG_2D>;
power-domain-names = "core0", "core1", "core2";
operating-points-v2 = <&gpu_opp_table>;
};
mmsys: syscon@14000000 {
compatible = "mediatek,mt8183-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;