iwlwifi: pcie: enable LP XTAL to reduce power consumption
1. Enable LP XTAL to avoid HW bug where device may consume much power if FW is not loaded after device reset. LP XTAL is disabled by default after device HW reset. Configure device's "persistence" mode to avoid resetting XTAL again when SHRD_HW_RST occurs in S3. 2. Add methods to access SHR (shared block memory space) directly from PCI bus w/o need to power up MAC HW. Shared internal registers (e.g. SHR_APMG_GP1, SHR_APMG_XTAL_CFG)can be accessed directly from PCI bus through SHR arbiter even when MAC HW is powered down. This is possible due to indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers. Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW need not be powered up so no "grab inc access" is required. For example, to read from SHR_APMG_GP1 register (0x1DC), first, write to the control register: HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register) HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access) second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0]. To write the register, first, write to the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then: HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register) HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access) Signed-off-by: Alexander Bondar <alexander.bondar@intel.com> Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
This commit is contained in:
Alexander Bondar
Emmanuel Grumbach
parent
8ea0c68fe5
commit
a812cba9bb
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@ -134,6 +134,7 @@ const struct iwl_cfg iwl7260_2ac_cfg = {
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.nvm_ver = IWL7260_NVM_VERSION,
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.nvm_calib_ver = IWL7260_TX_POWER_VERSION,
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.host_interrupt_operation_mode = true,
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.lp_xtal_workaround = true,
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};
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const struct iwl_cfg iwl7260_2ac_cfg_high_temp = {
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@ -145,6 +146,7 @@ const struct iwl_cfg iwl7260_2ac_cfg_high_temp = {
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.nvm_calib_ver = IWL7260_TX_POWER_VERSION,
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.high_temp = true,
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.host_interrupt_operation_mode = true,
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.lp_xtal_workaround = true,
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};
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const struct iwl_cfg iwl7260_2n_cfg = {
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@ -155,6 +157,7 @@ const struct iwl_cfg iwl7260_2n_cfg = {
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.nvm_ver = IWL7260_NVM_VERSION,
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.nvm_calib_ver = IWL7260_TX_POWER_VERSION,
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.host_interrupt_operation_mode = true,
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.lp_xtal_workaround = true,
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};
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const struct iwl_cfg iwl7260_n_cfg = {
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@ -165,6 +168,7 @@ const struct iwl_cfg iwl7260_n_cfg = {
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.nvm_ver = IWL7260_NVM_VERSION,
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.nvm_calib_ver = IWL7260_TX_POWER_VERSION,
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.host_interrupt_operation_mode = true,
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.lp_xtal_workaround = true,
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};
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const struct iwl_cfg iwl3160_2ac_cfg = {
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@ -262,6 +262,7 @@ struct iwl_cfg {
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bool high_temp;
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bool d0i3;
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u8 nvm_hw_section_num;
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bool lp_xtal_workaround;
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const struct iwl_pwr_tx_backoff *pwr_tx_backoffs;
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};
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@ -138,6 +138,13 @@
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/* Analog phase-lock-loop configuration */
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#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
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/*
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* CSR HW resources monitor registers
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*/
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#define CSR_MONITOR_CFG_REG (CSR_BASE+0x214)
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#define CSR_MONITOR_STATUS_REG (CSR_BASE+0x228)
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#define CSR_MONITOR_XTAL_RESOURCES (0x00000010)
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/*
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* CSR Hardware Revision Workaround Register. Indicates hardware rev;
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* "step" determines CCK backoff for txpower calculation. Used for 4965 only.
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@ -173,6 +180,7 @@
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#define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
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#define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
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#define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
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#define CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */
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#define CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
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#define CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
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@ -240,6 +248,7 @@
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* 001 -- MAC power-down
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* 010 -- PHY (radio) power-down
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* 011 -- Error
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* 10: XTAL ON request
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* 9-6: SYS_CONFIG
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* Indicates current system configuration, reflecting pins on chip
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* as forced high/low by device circuit board.
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@ -271,6 +280,7 @@
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#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
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#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
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#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
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#define CSR_GP_CNTRL_REG_FLAG_XTAL_ON (0x00000400)
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#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
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@ -395,6 +405,34 @@
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#define CSR_DRAM_INT_TBL_ENABLE (1 << 31)
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#define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
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/*
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* SHR target access (Shared block memory space)
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*
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* Shared internal registers can be accessed directly from PCI bus through SHR
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* arbiter without need for the MAC HW to be powered up. This is possible due to
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* indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and
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* HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers.
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*
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* Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW
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* need not be powered up so no "grab inc access" is required.
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*/
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/*
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* Registers for accessing shared registers (e.g. SHR_APMG_GP1,
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* SHR_APMG_XTAL_CFG). For example, to read from SHR_APMG_GP1 register (0x1DC),
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* first, write to the control register:
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* HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
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* HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access)
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* second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0].
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*
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* To write the register, first, write to the data register
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* HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then:
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* HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
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* HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access)
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*/
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#define HEEP_CTRL_WRD_PCIEX_CTRL_REG (CSR_BASE+0x0ec)
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#define HEEP_CTRL_WRD_PCIEX_DATA_REG (CSR_BASE+0x0f4)
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/*
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* HBUS (Host-side Bus)
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*
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@ -93,14 +93,14 @@ int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask,
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}
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IWL_EXPORT_SYMBOL(iwl_poll_direct_bit);
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static inline u32 __iwl_read_prph(struct iwl_trans *trans, u32 ofs)
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u32 __iwl_read_prph(struct iwl_trans *trans, u32 ofs)
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{
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u32 val = iwl_trans_read_prph(trans, ofs);
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trace_iwlwifi_dev_ioread_prph32(trans->dev, ofs, val);
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return val;
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}
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static inline void __iwl_write_prph(struct iwl_trans *trans, u32 ofs, u32 val)
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void __iwl_write_prph(struct iwl_trans *trans, u32 ofs, u32 val)
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{
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trace_iwlwifi_dev_iowrite_prph32(trans->dev, ofs, val);
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iwl_trans_write_prph(trans, ofs, val);
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@ -70,7 +70,9 @@ u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg);
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void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value);
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u32 __iwl_read_prph(struct iwl_trans *trans, u32 ofs);
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u32 iwl_read_prph(struct iwl_trans *trans, u32 ofs);
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void __iwl_write_prph(struct iwl_trans *trans, u32 ofs, u32 val);
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void iwl_write_prph(struct iwl_trans *trans, u32 ofs, u32 val);
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int iwl_poll_prph_bit(struct iwl_trans *trans, u32 addr,
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u32 bits, u32 mask, int timeout);
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@ -95,7 +95,8 @@
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#define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
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#define APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
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#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
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#define APMG_PCIDEV_STT_VAL_PERSIST_DIS (0x00000200)
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#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
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#define APMG_RTC_INT_STT_RFKILL (0x10000000)
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@ -105,6 +106,26 @@
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/* Device NMI register */
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#define DEVICE_SET_NMI_REG 0x00a01c30
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/* Shared registers (0x0..0x3ff, via target indirect or periphery */
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#define SHR_BASE 0x00a10000
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/* Shared GP1 register */
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#define SHR_APMG_GP1_REG 0x01dc
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#define SHR_APMG_GP1_REG_PRPH (SHR_BASE + SHR_APMG_GP1_REG)
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#define SHR_APMG_GP1_WF_XTAL_LP_EN 0x00000004
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#define SHR_APMG_GP1_CHICKEN_BIT_SELECT 0x80000000
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/* Shared DL_CFG register */
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#define SHR_APMG_DL_CFG_REG 0x01c4
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#define SHR_APMG_DL_CFG_REG_PRPH (SHR_BASE + SHR_APMG_DL_CFG_REG)
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#define SHR_APMG_DL_CFG_RTCS_CLK_SELECTOR_MSK 0x000000c0
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#define SHR_APMG_DL_CFG_RTCS_CLK_INTERNAL_XTAL 0x00000080
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#define SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP 0x00000100
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/* Shared APMG_XTAL_CFG register */
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#define SHR_APMG_XTAL_CFG_REG 0x1c0
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#define SHR_APMG_XTAL_CFG_XTAL_ON_REQ 0x80000000
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/*
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* Device reset for family 8000
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* write to bit 24 in order to reset the CPU
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@ -75,6 +75,20 @@
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#include "iwl-agn-hw.h"
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#include "internal.h"
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static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
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{
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iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
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((reg & 0x0000ffff) | (2 << 28)));
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return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
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}
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static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
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{
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iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
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iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
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((reg & 0x0000ffff) | (3 << 28)));
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}
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static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
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{
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if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
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@ -229,6 +243,116 @@ out:
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return ret;
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}
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/*
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* Enable LP XTAL to avoid HW bug where device may consume much power if
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* FW is not loaded after device reset. LP XTAL is disabled by default
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* after device HW reset. Do it only if XTAL is fed by internal source.
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* Configure device's "persistence" mode to avoid resetting XTAL again when
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* SHRD_HW_RST occurs in S3.
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*/
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static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
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{
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int ret;
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u32 apmg_gp1_reg;
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u32 apmg_xtal_cfg_reg;
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u32 dl_cfg_reg;
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/* Force XTAL ON */
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__iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
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/* Reset entire device - do controller reset (results in SHRD_HW_RST) */
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iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
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udelay(10);
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/*
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* Set "initialization complete" bit to move adapter from
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* D0U* --> D0A* (powered-up active) state.
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*/
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iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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/*
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* Wait for clock stabilization; once stabilized, access to
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* device-internal resources is possible.
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*/
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ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
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CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
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25000);
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if (WARN_ON(ret < 0)) {
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IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
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/* Release XTAL ON request */
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__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
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return;
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}
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/*
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* Clear "disable persistence" to avoid LP XTAL resetting when
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* SHRD_HW_RST is applied in S3.
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*/
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iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
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APMG_PCIDEV_STT_VAL_PERSIST_DIS);
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/*
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* Force APMG XTAL to be active to prevent its disabling by HW
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* caused by APMG idle state.
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*/
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apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
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SHR_APMG_XTAL_CFG_REG);
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iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
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apmg_xtal_cfg_reg |
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SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
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/*
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* Reset entire device again - do controller reset (results in
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* SHRD_HW_RST). Turn MAC off before proceeding.
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*/
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iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
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udelay(10);
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/* Enable LP XTAL by indirect access through CSR */
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apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
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iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
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SHR_APMG_GP1_WF_XTAL_LP_EN |
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SHR_APMG_GP1_CHICKEN_BIT_SELECT);
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/* Clear delay line clock power up */
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dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
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iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
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~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
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/*
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* Enable persistence mode to avoid LP XTAL resetting when
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* SHRD_HW_RST is applied in S3.
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*/
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iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
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CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
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/*
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* Clear "initialization complete" bit to move adapter from
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* D0A* (powered-up Active) --> D0U* (Uninitialized) state.
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*/
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iwl_clear_bit(trans, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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/* Activates XTAL resources monitor */
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__iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
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CSR_MONITOR_XTAL_RESOURCES);
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/* Release XTAL ON request */
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__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
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udelay(10);
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/* Release APMG XTAL */
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iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
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apmg_xtal_cfg_reg &
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~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
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}
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static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
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{
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int ret = 0;
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@ -256,6 +380,11 @@ static void iwl_pcie_apm_stop(struct iwl_trans *trans)
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/* Stop device's DMA activity */
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iwl_pcie_apm_stop_master(trans);
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if (trans->cfg->lp_xtal_workaround) {
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iwl_pcie_apm_lp_xtal_enable(trans);
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return;
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}
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/* Reset the entire device */
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iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
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@ -1208,6 +1337,7 @@ static const char *get_csr_string(int cmd)
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IWL_CMD(CSR_GIO_CHICKEN_BITS);
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IWL_CMD(CSR_ANA_PLL_CFG);
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IWL_CMD(CSR_HW_REV_WA_REG);
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IWL_CMD(CSR_MONITOR_STATUS_REG);
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IWL_CMD(CSR_DBG_HPET_MEM_REG);
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default:
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return "UNKNOWN";
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@ -1240,6 +1370,7 @@ void iwl_pcie_dump_csr(struct iwl_trans *trans)
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CSR_DRAM_INT_TBL_REG,
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CSR_GIO_CHICKEN_BITS,
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CSR_ANA_PLL_CFG,
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CSR_MONITOR_STATUS_REG,
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CSR_HW_REV_WA_REG,
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CSR_DBG_HPET_MEM_REG
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};
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