x86/sev-es: Add CPUID handling to #VC handler
Handle #VC exceptions caused by CPUID instructions. These happen in early boot code when the KASLR code checks for RDTSC. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> [ jroedel@suse.de: Adapt to #VC handling framework ] Co-developed-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20200907131613.12703-28-joro@8bytes.org
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@ -16,6 +16,7 @@
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#include <asm/trapnr.h>
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#include <asm/trap_pf.h>
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#include <asm/msr-index.h>
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#include <asm/fpu/xcr.h>
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#include <asm/ptrace.h>
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#include <asm/svm.h>
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@ -183,6 +184,9 @@ void do_boot_stage2_vc(struct pt_regs *regs, unsigned long exit_code)
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case SVM_EXIT_IOIO:
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result = vc_handle_ioio(boot_ghcb, &ctxt);
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break;
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case SVM_EXIT_CPUID:
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result = vc_handle_cpuid(boot_ghcb, &ctxt);
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break;
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default:
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result = ES_UNSUPPORTED;
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break;
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@ -432,3 +432,38 @@ static enum es_result vc_handle_ioio(struct ghcb *ghcb, struct es_em_ctxt *ctxt)
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return ret;
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}
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static enum es_result vc_handle_cpuid(struct ghcb *ghcb,
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struct es_em_ctxt *ctxt)
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{
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struct pt_regs *regs = ctxt->regs;
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u32 cr4 = native_read_cr4();
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enum es_result ret;
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ghcb_set_rax(ghcb, regs->ax);
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ghcb_set_rcx(ghcb, regs->cx);
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if (cr4 & X86_CR4_OSXSAVE)
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/* Safe to read xcr0 */
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ghcb_set_xcr0(ghcb, xgetbv(XCR_XFEATURE_ENABLED_MASK));
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else
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/* xgetbv will cause #GP - use reset value for xcr0 */
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ghcb_set_xcr0(ghcb, 1);
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ret = sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_CPUID, 0, 0);
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if (ret != ES_OK)
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return ret;
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if (!(ghcb_rax_is_valid(ghcb) &&
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ghcb_rbx_is_valid(ghcb) &&
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ghcb_rcx_is_valid(ghcb) &&
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ghcb_rdx_is_valid(ghcb)))
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return ES_VMM_ERROR;
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regs->ax = ghcb->save.rax;
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regs->bx = ghcb->save.rbx;
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regs->cx = ghcb->save.rcx;
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regs->dx = ghcb->save.rdx;
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return ES_OK;
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}
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