From a7c18e5cbb23ec467fb0671ee72ee7790b37335e Mon Sep 17 00:00:00 2001 From: Fred Ai Date: Wed, 15 Dec 2021 22:08:24 -0800 Subject: [PATCH] mmc: sdhci-pci-o2micro: Restore the SD clock's base clock frequency Drop the SD clock's base clock for an SDR104 card, as frequency is wrong when inserting and SD2.0/SDR50 card. Signed-off-by: Fred Ai Acked-by: Adrian Hunter Link: https://lore.kernel.org/r/20211216060824.357-2-fred.ai@bayhubtech.com Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-pci-o2micro.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c index 56e9f93999c4..92c20cb8074a 100644 --- a/drivers/mmc/host/sdhci-pci-o2micro.c +++ b/drivers/mmc/host/sdhci-pci-o2micro.c @@ -578,6 +578,11 @@ static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock) if ((scratch_32 & 0xFFFF0000) != 0x2c280000) o2_pci_set_baseclk(chip, 0x2c280000); + } else { + pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); + + if ((scratch_32 & 0xFFFF0000) != 0x25100000) + o2_pci_set_baseclk(chip, 0x25100000); } pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &scratch_32);