drm/amdgpu: attempt xgmi perfmon re-arm on failed arm
The DF routines to arm xGMI performance will attempt to re-arm both on performance monitoring start and read on initial failure to arm. Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jonathan Kim
Alex Deucher
parent
5e9eec0707
commit
a7843c0379
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@ -183,6 +183,61 @@ static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_addr,
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spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
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}
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/* same as perfmon_wreg but return status on write value check */
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static int df_v3_6_perfmon_arm_with_status(struct amdgpu_device *adev,
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uint32_t lo_addr, uint32_t lo_val,
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uint32_t hi_addr, uint32_t hi_val)
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{
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unsigned long flags, address, data;
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uint32_t lo_val_rb, hi_val_rb;
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address = adev->nbio.funcs->get_pcie_index_offset(adev);
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data = adev->nbio.funcs->get_pcie_data_offset(adev);
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spin_lock_irqsave(&adev->pcie_idx_lock, flags);
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WREG32(address, lo_addr);
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WREG32(data, lo_val);
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WREG32(address, hi_addr);
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WREG32(data, hi_val);
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WREG32(address, lo_addr);
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lo_val_rb = RREG32(data);
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WREG32(address, hi_addr);
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hi_val_rb = RREG32(data);
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spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
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if (!(lo_val == lo_val_rb && hi_val == hi_val_rb))
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return -EBUSY;
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return 0;
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}
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/*
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* retry arming counters every 100 usecs within 1 millisecond interval.
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* if retry fails after time out, return error.
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*/
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#define ARM_RETRY_USEC_TIMEOUT 1000
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#define ARM_RETRY_USEC_INTERVAL 100
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static int df_v3_6_perfmon_arm_with_retry(struct amdgpu_device *adev,
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uint32_t lo_addr, uint32_t lo_val,
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uint32_t hi_addr, uint32_t hi_val)
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{
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int countdown = ARM_RETRY_USEC_TIMEOUT;
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while (countdown) {
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if (!df_v3_6_perfmon_arm_with_status(adev, lo_addr, lo_val,
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hi_addr, hi_val))
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break;
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countdown -= ARM_RETRY_USEC_INTERVAL;
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udelay(ARM_RETRY_USEC_INTERVAL);
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}
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return countdown > 0 ? 0 : -ETIME;
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}
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/* get the number of df counters available */
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static ssize_t df_v3_6_get_df_cntr_avail(struct device *dev,
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struct device_attribute *attr,
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@ -334,20 +389,20 @@ static void df_v3_6_pmc_get_addr(struct amdgpu_device *adev,
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switch (target_cntr) {
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case 0:
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*lo_base_addr = is_ctrl ? smnPerfMonCtlLo0 : smnPerfMonCtrLo0;
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*hi_base_addr = is_ctrl ? smnPerfMonCtlHi0 : smnPerfMonCtrHi0;
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*lo_base_addr = is_ctrl ? smnPerfMonCtlLo4 : smnPerfMonCtrLo4;
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*hi_base_addr = is_ctrl ? smnPerfMonCtlHi4 : smnPerfMonCtrHi4;
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break;
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case 1:
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*lo_base_addr = is_ctrl ? smnPerfMonCtlLo1 : smnPerfMonCtrLo1;
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*hi_base_addr = is_ctrl ? smnPerfMonCtlHi1 : smnPerfMonCtrHi1;
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*lo_base_addr = is_ctrl ? smnPerfMonCtlLo5 : smnPerfMonCtrLo5;
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*hi_base_addr = is_ctrl ? smnPerfMonCtlHi5 : smnPerfMonCtrHi5;
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break;
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case 2:
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*lo_base_addr = is_ctrl ? smnPerfMonCtlLo2 : smnPerfMonCtrLo2;
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*hi_base_addr = is_ctrl ? smnPerfMonCtlHi2 : smnPerfMonCtrHi2;
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*lo_base_addr = is_ctrl ? smnPerfMonCtlLo6 : smnPerfMonCtrLo6;
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*hi_base_addr = is_ctrl ? smnPerfMonCtlHi6 : smnPerfMonCtrHi6;
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break;
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case 3:
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*lo_base_addr = is_ctrl ? smnPerfMonCtlLo3 : smnPerfMonCtrLo3;
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*hi_base_addr = is_ctrl ? smnPerfMonCtlHi3 : smnPerfMonCtrHi3;
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*lo_base_addr = is_ctrl ? smnPerfMonCtlLo7 : smnPerfMonCtrLo7;
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*hi_base_addr = is_ctrl ? smnPerfMonCtlHi7 : smnPerfMonCtrHi7;
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break;
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}
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@ -422,6 +477,44 @@ static int df_v3_6_pmc_add_cntr(struct amdgpu_device *adev,
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return -ENOSPC;
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}
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#define DEFERRED_ARM_MASK (1 << 31)
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static int df_v3_6_pmc_set_deferred(struct amdgpu_device *adev,
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uint64_t config, bool is_deferred)
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{
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int target_cntr;
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target_cntr = df_v3_6_pmc_config_2_cntr(adev, config);
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if (target_cntr < 0)
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return -EINVAL;
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if (is_deferred)
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adev->df_perfmon_config_assign_mask[target_cntr] |=
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DEFERRED_ARM_MASK;
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else
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adev->df_perfmon_config_assign_mask[target_cntr] &=
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~DEFERRED_ARM_MASK;
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return 0;
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}
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static bool df_v3_6_pmc_is_deferred(struct amdgpu_device *adev,
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uint64_t config)
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{
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int target_cntr;
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target_cntr = df_v3_6_pmc_config_2_cntr(adev, config);
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/*
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* we never get target_cntr < 0 since this funciton is only called in
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* pmc_count for now but we should check anyways.
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*/
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return (target_cntr >= 0 &&
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(adev->df_perfmon_config_assign_mask[target_cntr]
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& DEFERRED_ARM_MASK));
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}
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/* release performance counter */
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static void df_v3_6_pmc_release_cntr(struct amdgpu_device *adev,
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uint64_t config)
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@ -451,29 +544,33 @@ static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config,
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int is_enable)
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{
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uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
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int ret = 0;
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int err = 0, ret = 0;
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switch (adev->asic_type) {
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case CHIP_VEGA20:
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if (is_enable)
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return df_v3_6_pmc_add_cntr(adev, config);
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df_v3_6_reset_perfmon_cntr(adev, config);
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if (is_enable) {
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ret = df_v3_6_pmc_add_cntr(adev, config);
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} else {
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ret = df_v3_6_pmc_get_ctrl_settings(adev,
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ret = df_v3_6_pmc_get_ctrl_settings(adev,
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config,
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&lo_base_addr,
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&hi_base_addr,
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&lo_val,
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&hi_val);
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if (ret)
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return ret;
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if (ret)
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return ret;
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df_v3_6_perfmon_wreg(adev, lo_base_addr, lo_val,
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hi_base_addr, hi_val);
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}
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err = df_v3_6_perfmon_arm_with_retry(adev,
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lo_base_addr,
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lo_val,
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hi_base_addr,
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hi_val);
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if (err)
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ret = df_v3_6_pmc_set_deferred(adev, config, true);
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break;
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default:
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@ -501,7 +598,7 @@ static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config,
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if (ret)
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return ret;
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df_v3_6_perfmon_wreg(adev, lo_base_addr, 0, hi_base_addr, 0);
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df_v3_6_reset_perfmon_cntr(adev, config);
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if (is_disable)
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df_v3_6_pmc_release_cntr(adev, config);
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@ -518,18 +615,29 @@ static void df_v3_6_pmc_get_count(struct amdgpu_device *adev,
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uint64_t config,
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uint64_t *count)
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{
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uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
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uint32_t lo_base_addr, hi_base_addr, lo_val = 0, hi_val = 0;
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*count = 0;
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switch (adev->asic_type) {
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case CHIP_VEGA20:
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df_v3_6_pmc_get_read_settings(adev, config, &lo_base_addr,
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&hi_base_addr);
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if ((lo_base_addr == 0) || (hi_base_addr == 0))
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return;
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/* rearm the counter or throw away count value on failure */
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if (df_v3_6_pmc_is_deferred(adev, config)) {
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int rearm_err = df_v3_6_perfmon_arm_with_status(adev,
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lo_base_addr, lo_val,
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hi_base_addr, hi_val);
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if (rearm_err)
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return;
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df_v3_6_pmc_set_deferred(adev, config, false);
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}
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df_v3_6_perfmon_rreg(adev, lo_base_addr, &lo_val,
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hi_base_addr, &hi_val);
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@ -542,7 +650,6 @@ static void df_v3_6_pmc_get_count(struct amdgpu_device *adev,
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config, lo_base_addr, hi_base_addr, lo_val, hi_val);
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break;
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default:
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break;
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}
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