From a781d1e5ff6277f80ff3c9503775521bc64cf131 Mon Sep 17 00:00:00 2001 From: Matt Fleming Date: Fri, 4 Dec 2009 16:18:11 +0900 Subject: [PATCH] sh: Drop associative writes for SH-4 cache flushes. When flushing/invalidating the icache/dcache via the memory-mapped IC/OC address arrays, the associative bit should only be used in conjunction with virtual addresses. However, we currently flush cache lines based on physical address, so stop using the associative bit. It is a better strategy to use non-associative writes (and physical tags) for flushing the caches anyway, because flushing by virtual address (as with the A-bit set) requires a valid TLB entry for that virtual address. If one does not exist in the TLB no exception is generated and the flush is silently ignored. This is also future-proofing for SH-4A parts which are gradually phasing out associative writes to the cache array due to the aforementioned case of certain flushes silently turning in to nops. Signed-off-by: Matt Fleming Signed-off-by: Paul Mundt --- arch/sh/mm/cache-sh4.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c index 6bfd08d5fb81..f36a08bf3d5c 100644 --- a/arch/sh/mm/cache-sh4.c +++ b/arch/sh/mm/cache-sh4.c @@ -98,7 +98,7 @@ static inline void flush_cache_one(unsigned long start, unsigned long phys) exec_offset = cached_to_uncached; local_irq_save(flags); - __flush_cache_one(start | SH_CACHE_ASSOC, phys, exec_offset); + __flush_cache_one(start, phys, exec_offset); local_irq_restore(flags); } @@ -123,7 +123,7 @@ static void sh4_flush_dcache_page(void *arg) /* Loop all the D-cache */ n = boot_cpu_data.dcache.n_aliases; - for (i = 0; i <= n; i++, addr += PAGE_SIZE) + for (i = 0; i < n; i++, addr += PAGE_SIZE) flush_cache_one(addr, phys); }