ARM: shmobile: r8a73a4: Common clock framework DT description
Declares all r8a73a4 clocks supported by the legacy clock framework. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Ulrich Hecht
Simon Horman
parent
bdba0101c7
commit
a76809a329
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@ -9,6 +9,7 @@
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* kind, whether express or implied.
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*/
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#include <dt-bindings/clock/r8a73a4-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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@ -377,4 +378,297 @@
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<0 0xf1006000 0 0x2000>;
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interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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clocks {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* External root clocks */
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extalr_clk: extalr_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "extalr";
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};
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extal1_clk: extal1_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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clock-output-names = "extal1";
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};
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extal2_clk: extal2_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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clock-output-names = "extal2";
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};
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fsiack_clk: fsiack_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board. */
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clock-frequency = <0>;
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clock-output-names = "fsiack";
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};
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fsibck_clk: fsibck_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board. */
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clock-frequency = <0>;
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clock-output-names = "fsibck";
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};
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/* Special CPG clocks */
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,r8a73a4-cpg-clocks";
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reg = <0 0xe6150000 0 0x10000>;
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clocks = <&extal1_clk>, <&extal2_clk>;
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#clock-cells = <1>;
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clock-output-names = "main", "pll0", "pll1", "pll2",
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"pll2s", "pll2h", "z", "z2",
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"i", "m3", "b", "m1", "m2",
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"zx", "zs", "hp";
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};
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/* Variable factor clocks (DIV6) */
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zb_clk: zb_clk@e6150010 {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150010 0 4>;
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clocks = <&pll1_div2_clk>, <0>,
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<&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
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#clock-cells = <0>;
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clock-output-names = "zb";
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};
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sdhi0_clk: sdhi0_clk@e6150074 {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150074 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<0>, <&extal2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sdhi0ck";
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};
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sdhi1_clk: sdhi1_clk@e6150078 {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150078 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<0>, <&extal2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sdhi1ck";
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};
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sdhi2_clk: sdhi2_clk@e615007c {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe615007c 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<0>, <&extal2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sdhi2ck";
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};
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mmc0_clk: mmc0_clk@e6150240 {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150240 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<0>, <&extal2_clk>;
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#clock-cells = <0>;
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clock-output-names = "mmc0";
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};
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mmc1_clk: mmc1_clk@e6150244 {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150244 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<0>, <&extal2_clk>;
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#clock-cells = <0>;
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clock-output-names = "mmc1";
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};
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vclk1_clk: vclk1_clk@e6150008 {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150008 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<0>, <&extal2_clk>, <&main_div2_clk>,
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<&extalr_clk>, <0>, <0>;
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#clock-cells = <0>;
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clock-output-names = "vclk1";
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};
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vclk2_clk: vclk2_clk@e615000c {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe615000c 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<0>, <&extal2_clk>, <&main_div2_clk>,
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<&extalr_clk>, <0>, <0>;
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#clock-cells = <0>;
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clock-output-names = "vclk2";
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};
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vclk3_clk: vclk3_clk@e615001c {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe615001c 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<0>, <&extal2_clk>, <&main_div2_clk>,
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<&extalr_clk>, <0>, <0>;
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#clock-cells = <0>;
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clock-output-names = "vclk3";
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};
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vclk4_clk: vclk4_clk@e6150014 {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150014 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<0>, <&extal2_clk>, <&main_div2_clk>,
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<&extalr_clk>, <0>, <0>;
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#clock-cells = <0>;
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clock-output-names = "vclk4";
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};
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vclk5_clk: vclk5_clk@e6150034 {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150034 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<0>, <&extal2_clk>, <&main_div2_clk>,
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<&extalr_clk>, <0>, <0>;
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#clock-cells = <0>;
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clock-output-names = "vclk5";
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};
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fsia_clk: fsia_clk@e6150018 {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150018 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<&fsiack_clk>, <0>;
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#clock-cells = <0>;
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clock-output-names = "fsia";
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};
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fsib_clk: fsib_clk@e6150090 {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150090 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<&fsibck_clk>, <0>;
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#clock-cells = <0>;
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clock-output-names = "fsib";
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};
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mp_clk: mp_clk@e6150080 {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150080 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<&extal2_clk>, <&extal2_clk>;
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#clock-cells = <0>;
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clock-output-names = "mp";
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};
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m4_clk: m4_clk@e6150098 {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150098 0 4>;
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clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
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#clock-cells = <0>;
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clock-output-names = "m4";
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};
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hsi_clk: hsi_clk@e615026c {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe615026c 0 4>;
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clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
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<&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
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#clock-cells = <0>;
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clock-output-names = "hsi";
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};
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spuv_clk: spuv_clk@e6150094 {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150094 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<&extal2_clk>, <&extal2_clk>;
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#clock-cells = <0>;
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clock-output-names = "spuv";
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};
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/* Fixed factor clocks */
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main_div2_clk: main_div2_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "main_div2";
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};
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pll0_div2_clk: pll0_div2_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "pll0_div2";
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};
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pll1_div2_clk: pll1_div2_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "pll1_div2";
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};
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extal1_div2_clk: extal1_div2_clk {
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compatible = "fixed-factor-clock";
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clocks = <&extal1_clk>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "extal1_div2";
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};
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/* Gate clocks */
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mstp2_clks: mstp2_clks@e6150138 {
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compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
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clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
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<&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
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#clock-cells = <1>;
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clock-indices = <
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R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
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R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
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R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
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R8A73A4_CLK_DMAC
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>;
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clock-output-names =
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"scifa0", "scifa1", "scifb0", "scifb1",
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"scifb2", "scifb3", "dmac";
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};
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mstp3_clks: mstp3_clks@e615013c {
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compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
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clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>,
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<&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>,
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<&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
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<&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks
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R8A73A4_CLK_HP>, <&cpg_clocks
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R8A73A4_CLK_HP>, <&extalr_clk>;
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#clock-cells = <1>;
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clock-indices = <
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R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1
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R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1
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R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0
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R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7
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R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1
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R8A73A4_CLK_CMT1
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>;
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clock-output-names =
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"iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0",
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"mmcif0", "iic6", "iic7", "iic0", "iic1",
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"cmt1";
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};
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mstp4_clks: mstp4_clks@e6150140 {
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compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
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clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
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<&cpg_clocks R8A73A4_CLK_HP>;
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#clock-cells = <1>;
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clock-indices = <
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R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4
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R8A73A4_CLK_IIC3
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>;
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clock-output-names =
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"iic5", "iic4", "iic3";
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};
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mstp5_clks: mstp5_clks@e6150144 {
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compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
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clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
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#clock-cells = <1>;
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clock-indices = <
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R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8
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>;
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clock-output-names =
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"thermal", "iic8";
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};
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};
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};
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