drm/amdgpu/vcn3.0: add software ring share memory support
Support software ring share memory with vcn firmware. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -170,6 +170,7 @@ static int vcn_v3_0_sw_init(void *handle)
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}
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}
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for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
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for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
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volatile struct amdgpu_fw_shared *fw_shared;
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if (adev->vcn.harvest_config & (1 << i))
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if (adev->vcn.harvest_config & (1 << i))
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continue;
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continue;
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@ -234,6 +235,10 @@ static int vcn_v3_0_sw_init(void *handle)
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if (r)
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if (r)
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return r;
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return r;
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}
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}
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fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
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fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG);
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fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED);
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}
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}
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if (amdgpu_sriov_vf(adev)) {
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if (amdgpu_sriov_vf(adev)) {
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@ -257,7 +262,17 @@ static int vcn_v3_0_sw_init(void *handle)
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static int vcn_v3_0_sw_fini(void *handle)
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static int vcn_v3_0_sw_fini(void *handle)
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{
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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int r;
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int i, r;
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for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
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volatile struct amdgpu_fw_shared *fw_shared;
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if (adev->vcn.harvest_config & (1 << i))
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continue;
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fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
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fw_shared->present_flag_0 = 0;
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fw_shared->sw_ring.is_enabled = false;
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}
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if (amdgpu_sriov_vf(adev))
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if (amdgpu_sriov_vf(adev))
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amdgpu_virt_free_mm_table(adev);
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amdgpu_virt_free_mm_table(adev);
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@ -467,6 +482,15 @@ static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst)
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upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
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upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
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WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0);
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WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0);
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WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
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WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
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/* non-cache window */
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WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
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lower_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr));
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WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
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upper_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr));
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WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
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WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0,
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AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
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}
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}
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static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
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static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
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@ -549,13 +573,16 @@ static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
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/* non-cache window */
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/* non-cache window */
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WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
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WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
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VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
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VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
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lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);
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WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
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WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
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VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
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VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
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upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);
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WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
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WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
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VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
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VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
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WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
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WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
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VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
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VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0),
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AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
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}
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}
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static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
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static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
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