V4L/DVB (3795): Fix for CX24123 & low symbol rates
- fixed the reception of channels with low symbol rates. ( The VGA1 and VGA2 offsets recommended by cx24109 docs for symbol rates from 1 to 5 MSps do not work. I changed them to values found experimentally. The charge pump current and FILTUNE voltage are now set to values recommended in the docs. This improves reception for symbol rates < 15 MSps. The values written in the SYSSymbolRate registers are calculated with better precision. ) - fixed the cx24123_get_fec() function. It was returning the values for DCII mode. - removed some unused variables Signed-off-by: Vadim Catana <skystar at moldova.cc> Signed-off-by: Andrew de Quincey <adq_dvb@lidskialf.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
This commit is contained in:
Vadim Catana
Mauro Carvalho Chehab
parent
3a63fc4bfd
commit
a74b51fca9
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@ -29,6 +29,8 @@
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#include "dvb_frontend.h"
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#include "cx24123.h"
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#define XTAL 10111000
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static int debug;
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#define dprintk(args...) \
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do { \
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@ -52,6 +54,7 @@ struct cx24123_state
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u32 VGAarg;
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u32 bandselectarg;
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u32 pllarg;
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u32 FILTune;
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/* The Demod/Tuner can't easily provide these, we cache them */
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u32 currentfreq;
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@ -63,43 +66,33 @@ static struct
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{
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u32 symbolrate_low;
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u32 symbolrate_high;
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u32 VCAslope;
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u32 VCAoffset;
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u32 VGA1offset;
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u32 VGA2offset;
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u32 VCAprogdata;
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u32 VGAprogdata;
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u32 FILTune;
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} cx24123_AGC_vals[] =
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{
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{
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.symbolrate_low = 1000000,
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.symbolrate_high = 4999999,
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.VCAslope = 0x07,
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.VCAoffset = 0x0f,
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.VGA1offset = 0x1f8,
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.VGA2offset = 0x1f8,
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.VGAprogdata = (2 << 18) | (0x1f8 << 9) | 0x1f8,
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/* the specs recommend other values for VGA offsets,
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but tests show they are wrong */
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.VGAprogdata = (2 << 18) | (0x180 << 9) | 0x1e0,
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.VCAprogdata = (4 << 18) | (0x07 << 9) | 0x07,
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.FILTune = 0x280 /* 0.41 V */
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},
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{
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.symbolrate_low = 5000000,
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.symbolrate_high = 14999999,
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.VCAslope = 0x1f,
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.VCAoffset = 0x1f,
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.VGA1offset = 0x1e0,
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.VGA2offset = 0x180,
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.VGAprogdata = (2 << 18) | (0x180 << 9) | 0x1e0,
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.VCAprogdata = (4 << 18) | (0x07 << 9) | 0x1f,
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.FILTune = 0x317 /* 0.90 V */
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},
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{
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.symbolrate_low = 15000000,
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.symbolrate_high = 45000000,
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.VCAslope = 0x3f,
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.VCAoffset = 0x3f,
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.VGA1offset = 0x180,
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.VGA2offset = 0x100,
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.VGAprogdata = (2 << 18) | (0x100 << 9) | 0x180,
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.VCAprogdata = (4 << 18) | (0x07 << 9) | 0x3f,
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.FILTune = 0x146 /* 2.70 V */
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},
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};
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@ -112,90 +105,68 @@ static struct
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{
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u32 freq_low;
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u32 freq_high;
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u32 bandselect;
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u32 VCOdivider;
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u32 VCOnumber;
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u32 progdata;
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} cx24123_bandselect_vals[] =
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{
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{
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.freq_low = 950000,
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.freq_high = 1018999,
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.bandselect = 0x40,
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.VCOdivider = 4,
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.VCOnumber = 7,
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.progdata = (0 << 18) | (0 << 9) | 0x40,
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},
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{
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.freq_low = 1019000,
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.freq_high = 1074999,
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.bandselect = 0x80,
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.VCOdivider = 4,
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.VCOnumber = 8,
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.progdata = (0 << 18) | (0 << 9) | 0x80,
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},
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{
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.freq_low = 1075000,
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.freq_high = 1227999,
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.bandselect = 0x01,
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.VCOdivider = 2,
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.VCOnumber = 1,
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.progdata = (0 << 18) | (1 << 9) | 0x01,
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},
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{
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.freq_low = 1228000,
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.freq_high = 1349999,
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.bandselect = 0x02,
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.VCOdivider = 2,
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.VCOnumber = 2,
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.progdata = (0 << 18) | (1 << 9) | 0x02,
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},
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{
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.freq_low = 1350000,
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.freq_high = 1481999,
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.bandselect = 0x04,
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.VCOdivider = 2,
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.VCOnumber = 3,
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.progdata = (0 << 18) | (1 << 9) | 0x04,
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},
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{
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.freq_low = 1482000,
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.freq_high = 1595999,
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.bandselect = 0x08,
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.VCOdivider = 2,
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.VCOnumber = 4,
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.progdata = (0 << 18) | (1 << 9) | 0x08,
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},
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{
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.freq_low = 1596000,
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.freq_high = 1717999,
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.bandselect = 0x10,
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.VCOdivider = 2,
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.VCOnumber = 5,
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.progdata = (0 << 18) | (1 << 9) | 0x10,
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},
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{
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.freq_low = 1718000,
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.freq_high = 1855999,
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.bandselect = 0x20,
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.VCOdivider = 2,
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.VCOnumber = 6,
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.progdata = (0 << 18) | (1 << 9) | 0x20,
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},
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{
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.freq_low = 1856000,
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.freq_high = 2035999,
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.bandselect = 0x40,
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.VCOdivider = 2,
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.VCOnumber = 7,
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.progdata = (0 << 18) | (1 << 9) | 0x40,
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},
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{
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.freq_low = 2036000,
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.freq_high = 2149999,
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.bandselect = 0x80,
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.VCOdivider = 2,
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.VCOnumber = 8,
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.progdata = (0 << 18) | (1 << 9) | 0x80,
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},
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};
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@ -207,7 +178,6 @@ static struct {
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{
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{0x00, 0x03}, /* Reset system */
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{0x00, 0x00}, /* Clear reset */
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{0x01, 0x3b}, /* Apply sensible defaults, from an i2c sniffer */
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{0x03, 0x07},
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{0x04, 0x10},
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{0x05, 0x04},
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@ -217,7 +187,6 @@ static struct {
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{0x0f, 0xfe},
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{0x10, 0x01},
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{0x14, 0x01},
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{0x15, 0x98},
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{0x16, 0x00},
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{0x17, 0x01},
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{0x1b, 0x05},
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@ -226,8 +195,6 @@ static struct {
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{0x1e, 0x00},
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{0x20, 0x41},
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{0x21, 0x15},
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{0x27, 0x14},
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{0x28, 0x46},
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{0x29, 0x00},
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{0x2a, 0xb0},
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{0x2b, 0x73},
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@ -375,55 +342,103 @@ static int cx24123_set_fec(struct cx24123_state* state, fe_code_rate_t fec)
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static int cx24123_get_fec(struct cx24123_state* state, fe_code_rate_t *fec)
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{
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int ret;
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u8 val;
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ret = cx24123_readreg (state, 0x1b);
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if (ret < 0)
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return ret;
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val = ret & 0x07;
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switch (val) {
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ret = ret & 0x07;
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switch (ret) {
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case 1:
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*fec = FEC_1_2;
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break;
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case 3:
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case 2:
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*fec = FEC_2_3;
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break;
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case 4:
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case 3:
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*fec = FEC_3_4;
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break;
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case 5:
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case 4:
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*fec = FEC_4_5;
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break;
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case 6:
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case 5:
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*fec = FEC_5_6;
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break;
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case 6:
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*fec = FEC_6_7;
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break;
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case 7:
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*fec = FEC_7_8;
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break;
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case 2: /* *fec = FEC_3_5; break; */
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case 0: /* *fec = FEC_5_11; break; */
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*fec = FEC_AUTO;
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break;
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default:
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*fec = FEC_NONE; // can't happen
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printk("FEC_NONE ?\n");
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}
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return 0;
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}
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/* fixme: Symbol rates < 3MSps may not work because of precision loss */
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static int cx24123_set_symbolrate(struct cx24123_state* state, u32 srate)
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{
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u32 val;
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u32 tmp, sample_rate, ratio;
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u8 pll_mult;
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val = (srate / 1185) * 100;
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/* check if symbol rate is within limits */
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if ((srate > state->ops.info.symbol_rate_max) ||
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(srate < state->ops.info.symbol_rate_min))
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return -EOPNOTSUPP;;
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/* Compensate for scaling up, by removing 17 symbols per 1Msps */
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val = val - (17 * (srate / 1000000));
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/* choose the sampling rate high enough for the required operation,
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while optimizing the power consumed by the demodulator */
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if (srate < (XTAL*2)/2)
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pll_mult = 2;
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else if (srate < (XTAL*3)/2)
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pll_mult = 3;
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else if (srate < (XTAL*4)/2)
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pll_mult = 4;
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else if (srate < (XTAL*5)/2)
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pll_mult = 5;
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else if (srate < (XTAL*6)/2)
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pll_mult = 6;
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else if (srate < (XTAL*7)/2)
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pll_mult = 7;
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else if (srate < (XTAL*8)/2)
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pll_mult = 8;
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else
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pll_mult = 9;
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cx24123_writereg(state, 0x08, (val >> 16) & 0xff );
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cx24123_writereg(state, 0x09, (val >> 8) & 0xff );
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cx24123_writereg(state, 0x0a, (val ) & 0xff );
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sample_rate = pll_mult * XTAL;
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/*
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SYSSymbolRate[21:0] = (srate << 23) / sample_rate
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We have to use 32 bit unsigned arithmetic without precision loss.
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The maximum srate is 45000000 or 0x02AEA540. This number has
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only 6 clear bits on top, hence we can shift it left only 6 bits
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at a time. Borrowed from cx24110.c
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*/
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tmp = srate << 6;
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ratio = tmp / sample_rate;
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tmp = (tmp % sample_rate) << 6;
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ratio = (ratio << 6) + (tmp / sample_rate);
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tmp = (tmp % sample_rate) << 6;
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ratio = (ratio << 6) + (tmp / sample_rate);
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tmp = (tmp % sample_rate) << 5;
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ratio = (ratio << 5) + (tmp / sample_rate);
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cx24123_writereg(state, 0x01, pll_mult * 6);
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cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f );
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cx24123_writereg(state, 0x09, (ratio >> 8) & 0xff );
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cx24123_writereg(state, 0x0a, (ratio ) & 0xff );
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dprintk("%s: srate=%d, ratio=0x%08x, sample_rate=%i\n", __FUNCTION__, srate, ratio, sample_rate);
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return 0;
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}
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@ -437,6 +452,7 @@ static int cx24123_pll_calculate(struct dvb_frontend* fe, struct dvb_frontend_pa
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struct cx24123_state *state = fe->demodulator_priv;
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u32 ndiv = 0, adiv = 0, vco_div = 0;
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int i = 0;
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int pump = 2;
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/* Defaults for low freq, low rate */
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state->VCAarg = cx24123_AGC_vals[0].VCAprogdata;
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@ -444,13 +460,14 @@ static int cx24123_pll_calculate(struct dvb_frontend* fe, struct dvb_frontend_pa
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state->bandselectarg = cx24123_bandselect_vals[0].progdata;
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vco_div = cx24123_bandselect_vals[0].VCOdivider;
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/* For the given symbolerate, determine the VCA and VGA programming bits */
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/* For the given symbol rate, determine the VCA, VGA and FILTUNE programming bits */
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for (i = 0; i < sizeof(cx24123_AGC_vals) / sizeof(cx24123_AGC_vals[0]); i++)
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{
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if ((cx24123_AGC_vals[i].symbolrate_low <= p->u.qpsk.symbol_rate) &&
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(cx24123_AGC_vals[i].symbolrate_high >= p->u.qpsk.symbol_rate) ) {
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state->VCAarg = cx24123_AGC_vals[i].VCAprogdata;
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state->VGAarg = cx24123_AGC_vals[i].VGAprogdata;
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state->FILTune = cx24123_AGC_vals[i].FILTune;
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}
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}
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@ -461,21 +478,25 @@ static int cx24123_pll_calculate(struct dvb_frontend* fe, struct dvb_frontend_pa
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(cx24123_bandselect_vals[i].freq_high >= p->frequency) ) {
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state->bandselectarg = cx24123_bandselect_vals[i].progdata;
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vco_div = cx24123_bandselect_vals[i].VCOdivider;
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/* determine the charge pump current */
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if ( p->frequency < (cx24123_bandselect_vals[i].freq_low + cx24123_bandselect_vals[i].freq_high)/2 )
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pump = 0x01;
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else
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pump = 0x02;
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}
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}
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/* Determine the N/A dividers for the requested lband freq (in kHz). */
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/* Note: 10111 (kHz) is the Crystal Freq and divider of 10. */
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ndiv = ( ((p->frequency * vco_div) / (10111 / 10) / 2) / 32) & 0x1ff;
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adiv = ( ((p->frequency * vco_div) / (10111 / 10) / 2) % 32) & 0x1f;
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/* Note: the reference divider R=10, frequency is in KHz, XTAL is in Hz */
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ndiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) / 32) & 0x1ff;
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adiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) % 32) & 0x1f;
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if (adiv == 0)
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adiv++;
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ndiv++;
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/* determine the correct pll frequency values. */
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/* Command 11, refdiv 11, cpump polarity 1, cpump current 3mA 10. */
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state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) | (2 << 14);
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state->pllarg |= (ndiv << 5) | adiv;
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/* control bits 11, refdiv 11, charge pump polarity 1, charge pump current, ndiv, adiv */
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state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) | (pump << 14) | (ndiv << 5) | adiv;
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return 0;
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}
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@ -538,6 +559,9 @@ static int cx24123_pll_writereg(struct dvb_frontend* fe, struct dvb_frontend_par
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static int cx24123_pll_tune(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
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{
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struct cx24123_state *state = fe->demodulator_priv;
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u8 val;
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dprintk("frequency=%i\n", p->frequency);
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if (cx24123_pll_calculate(fe, p) != 0) {
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printk("%s: cx24123_pll_calcutate failed\n",__FUNCTION__);
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@ -552,6 +576,11 @@ static int cx24123_pll_tune(struct dvb_frontend* fe, struct dvb_frontend_paramet
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cx24123_pll_writereg(fe, p, state->bandselectarg);
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cx24123_pll_writereg(fe, p, state->pllarg);
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/* set the FILTUNE voltage */
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val = cx24123_readreg(state, 0x28) & ~0x3;
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cx24123_writereg(state, 0x27, state->FILTune >> 2);
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cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3));
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return 0;
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}
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@ -624,13 +653,81 @@ static int cx24123_set_voltage(struct dvb_frontend* fe, fe_sec_voltage_t voltage
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return 0;
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}
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static int cx24123_send_diseqc_msg(struct dvb_frontend* fe,
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struct dvb_diseqc_master_cmd *cmd)
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static int cx24123_send_diseqc_msg(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd *cmd)
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{
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/* fixme: Implement diseqc */
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printk("%s: No support yet\n",__FUNCTION__);
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struct cx24123_state *state = fe->demodulator_priv;
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int i, val;
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unsigned long timeout;
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dprintk("%s:\n",__FUNCTION__);
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/* check if continuous tone has been stoped */
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if (state->config->use_isl6421)
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val = cx24123_readlnbreg(state, 0x00) & 0x10;
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else
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val = cx24123_readreg(state, 0x29) & 0x10;
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if (val) {
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printk("%s: ERROR: attempt to send diseqc command before tone is off\n", __FUNCTION__);
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return -ENOTSUPP;
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}
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/* select tone mode */
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cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xf8);
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for (i = 0; i < cmd->msg_len; i++)
|
||||
cx24123_writereg(state, 0x2C + i, cmd->msg[i]);
|
||||
|
||||
val = cx24123_readreg(state, 0x29);
|
||||
cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) | ((cmd->msg_len-3) & 3));
|
||||
|
||||
timeout = jiffies + msecs_to_jiffies(100);
|
||||
while (!time_after(jiffies, timeout) && !(cx24123_readreg(state, 0x29) & 0x40))
|
||||
; // wait for LNB ready
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cx24123_diseqc_send_burst(struct dvb_frontend* fe, fe_sec_mini_cmd_t burst)
|
||||
{
|
||||
struct cx24123_state *state = fe->demodulator_priv;
|
||||
int val;
|
||||
unsigned long timeout;
|
||||
|
||||
dprintk("%s:\n", __FUNCTION__);
|
||||
|
||||
/* check if continuous tone has been stoped */
|
||||
if (state->config->use_isl6421)
|
||||
val = cx24123_readlnbreg(state, 0x00) & 0x10;
|
||||
else
|
||||
val = cx24123_readreg(state, 0x29) & 0x10;
|
||||
|
||||
|
||||
if (val) {
|
||||
printk("%s: ERROR: attempt to send diseqc command before tone is off\n", __FUNCTION__);
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
/* select tone mode */
|
||||
val = cx24123_readreg(state, 0x2a) & 0xf8;
|
||||
cx24123_writereg(state, 0x2a, val | 0x04);
|
||||
|
||||
val = cx24123_readreg(state, 0x29);
|
||||
|
||||
if (burst == SEC_MINI_A)
|
||||
cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00));
|
||||
else if (burst == SEC_MINI_B)
|
||||
cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08));
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
|
||||
timeout = jiffies + msecs_to_jiffies(100);
|
||||
while (!time_after(jiffies, timeout) && !(cx24123_readreg(state, 0x29) & 0x40))
|
||||
; // wait for LNB ready
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cx24123_read_status(struct dvb_frontend* fe, fe_status_t* status)
|
||||
|
|
@ -642,13 +739,15 @@ static int cx24123_read_status(struct dvb_frontend* fe, fe_status_t* status)
|
|||
|
||||
*status = 0;
|
||||
if (lock & 0x01)
|
||||
*status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
|
||||
*status |= FE_HAS_SIGNAL;
|
||||
if (sync & 0x02)
|
||||
*status |= FE_HAS_CARRIER;
|
||||
if (sync & 0x04)
|
||||
*status |= FE_HAS_VITERBI;
|
||||
if (sync & 0x08)
|
||||
*status |= FE_HAS_CARRIER;
|
||||
*status |= FE_HAS_SYNC;
|
||||
if (sync & 0x80)
|
||||
*status |= FE_HAS_SYNC | FE_HAS_LOCK;
|
||||
*status |= FE_HAS_LOCK;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -875,6 +974,7 @@ static struct dvb_frontend_ops cx24123_ops = {
|
|||
.read_snr = cx24123_read_snr,
|
||||
.read_ucblocks = cx24123_read_ucblocks,
|
||||
.diseqc_send_master_cmd = cx24123_send_diseqc_msg,
|
||||
.diseqc_send_burst = cx24123_diseqc_send_burst,
|
||||
.set_tone = cx24123_set_tone,
|
||||
.set_voltage = cx24123_set_voltage,
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue