drm/nouveau/bus: switch to subdev printk macros
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
60b29d2071
commit
a699a85add
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@ -27,20 +27,20 @@
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static void
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gf100_bus_intr(struct nvkm_subdev *subdev)
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{
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struct nvkm_bus *bus = nvkm_bus(subdev);
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struct nvkm_device *device = bus->subdev.device;
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struct nvkm_device *device = subdev->device;
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u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140);
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if (stat & 0x0000000e) {
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u32 addr = nvkm_rd32(device, 0x009084);
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u32 data = nvkm_rd32(device, 0x009088);
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nv_error(bus, "MMIO %s of 0x%08x FAULT at 0x%06x [ %s%s%s]\n",
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(addr & 0x00000002) ? "write" : "read", data,
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(addr & 0x00fffffc),
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(stat & 0x00000002) ? "!ENGINE " : "",
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(stat & 0x00000004) ? "IBUS " : "",
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(stat & 0x00000008) ? "TIMEOUT " : "");
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nvkm_error(subdev,
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"MMIO %s of %08x FAULT at %06x [ %s%s%s]\n",
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(addr & 0x00000002) ? "write" : "read", data,
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(addr & 0x00fffffc),
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(stat & 0x00000002) ? "!ENGINE " : "",
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(stat & 0x00000004) ? "IBUS " : "",
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(stat & 0x00000008) ? "TIMEOUT " : "");
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nvkm_wr32(device, 0x009084, 0x00000000);
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nvkm_wr32(device, 0x001100, (stat & 0x0000000e));
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@ -48,7 +48,7 @@ gf100_bus_intr(struct nvkm_subdev *subdev)
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}
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if (stat) {
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nv_error(bus, "unknown intr 0x%08x\n", stat);
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nvkm_error(subdev, "intr %08x\n", stat);
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nvkm_mask(device, 0x001140, stat, 0x00000000);
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}
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}
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@ -64,20 +64,21 @@ nvkm_hwsq_fini(struct nvkm_hwsq **phwsq, bool exec)
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int ret = 0, i;
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if (hwsq) {
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struct nvkm_bus *bus = hwsq->bus;
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struct nvkm_subdev *subdev = &bus->subdev;
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hwsq->c.size = (hwsq->c.size + 4) / 4;
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if (hwsq->c.size <= bus->hwsq_size) {
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if (exec)
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ret = bus->hwsq_exec(bus, (u32 *)hwsq->c.data,
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hwsq->c.size);
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hwsq->c.size);
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if (ret)
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nv_error(bus, "hwsq exec failed: %d\n", ret);
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nvkm_error(subdev, "hwsq exec failed: %d\n", ret);
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} else {
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nv_error(bus, "hwsq ucode too large\n");
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nvkm_error(subdev, "hwsq ucode too large\n");
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ret = -ENOSPC;
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}
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for (i = 0; ret && i < hwsq->c.size; i++)
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nv_error(bus, "\t0x%08x\n", ((u32 *)hwsq->c.data)[i]);
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nvkm_error(subdev, "\t%08x\n", ((u32 *)hwsq->c.data)[i]);
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*phwsq = NULL;
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kfree(hwsq);
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@ -88,7 +89,7 @@ nvkm_hwsq_fini(struct nvkm_hwsq **phwsq, bool exec)
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void
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nvkm_hwsq_wr32(struct nvkm_hwsq *hwsq, u32 addr, u32 data)
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{
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nv_debug(hwsq->bus, "R[%06x] = 0x%08x\n", addr, data);
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nvkm_debug(&hwsq->bus->subdev, "R[%06x] = %08x\n", addr, data);
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if (hwsq->data != data) {
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if ((data & 0xffff0000) != (hwsq->data & 0xffff0000)) {
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@ -113,7 +114,7 @@ nvkm_hwsq_wr32(struct nvkm_hwsq *hwsq, u32 addr, u32 data)
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void
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nvkm_hwsq_setf(struct nvkm_hwsq *hwsq, u8 flag, int data)
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{
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nv_debug(hwsq->bus, " FLAG[%02x] = %d\n", flag, data);
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nvkm_debug(&hwsq->bus->subdev, " FLAG[%02x] = %d\n", flag, data);
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flag += 0x80;
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if (data >= 0)
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flag += 0x20;
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@ -125,7 +126,7 @@ nvkm_hwsq_setf(struct nvkm_hwsq *hwsq, u8 flag, int data)
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void
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nvkm_hwsq_wait(struct nvkm_hwsq *hwsq, u8 flag, u8 data)
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{
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nv_debug(hwsq->bus, " WAIT[%02x] = %d\n", flag, data);
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nvkm_debug(&hwsq->bus->subdev, " WAIT[%02x] = %d\n", flag, data);
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hwsq_cmd(hwsq, 3, (u8[]){ 0x5f, flag, data });
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}
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@ -138,6 +139,6 @@ nvkm_hwsq_nsec(struct nvkm_hwsq *hwsq, u32 nsec)
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shift++;
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}
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nv_debug(hwsq->bus, " DELAY = %d ns\n", nsec);
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nvkm_debug(&hwsq->bus->subdev, " DELAY = %d ns\n", nsec);
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hwsq_cmd(hwsq, 1, (u8[]){ 0x00 | (shift << 2) | usec });
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}
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@ -24,29 +24,30 @@
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*/
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#include "nv04.h"
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#include <subdev/gpio.h>
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static void
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nv04_bus_intr(struct nvkm_subdev *subdev)
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{
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struct nvkm_bus *bus = nvkm_bus(subdev);
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struct nvkm_device *device = bus->subdev.device;
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struct nvkm_device *device = subdev->device;
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u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140);
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if (stat & 0x00000001) {
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nv_error(bus, "BUS ERROR\n");
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nvkm_error(subdev, "BUS ERROR\n");
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stat &= ~0x00000001;
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nvkm_wr32(device, 0x001100, 0x00000001);
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}
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if (stat & 0x00000110) {
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subdev = nvkm_subdev(subdev, NVDEV_SUBDEV_GPIO);
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if (subdev && subdev->intr)
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subdev->intr(subdev);
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struct nvkm_gpio *gpio = device->gpio;
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if (gpio && gpio->subdev.intr)
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gpio->subdev.intr(&gpio->subdev);
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stat &= ~0x00000110;
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nvkm_wr32(device, 0x001100, 0x00000110);
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}
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if (stat) {
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nv_error(bus, "unknown intr 0x%08x\n", stat);
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nvkm_error(subdev, "intr %08x\n", stat);
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nvkm_mask(device, 0x001140, stat, 0x00000000);
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}
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}
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@ -24,42 +24,44 @@
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*/
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#include "nv04.h"
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#include <subdev/gpio.h>
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#include <subdev/therm.h>
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static void
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nv31_bus_intr(struct nvkm_subdev *subdev)
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{
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struct nvkm_bus *bus = nvkm_bus(subdev);
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struct nvkm_device *device = bus->subdev.device;
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struct nvkm_device *device = subdev->device;
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u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140);
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u32 gpio = nvkm_rd32(device, 0x001104) & nvkm_rd32(device, 0x001144);
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if (gpio) {
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subdev = nvkm_subdev(bus, NVDEV_SUBDEV_GPIO);
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if (subdev && subdev->intr)
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subdev->intr(subdev);
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struct nvkm_gpio *gpio = device->gpio;
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if (gpio && gpio->subdev.intr)
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gpio->subdev.intr(&gpio->subdev);
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}
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if (stat & 0x00000008) { /* NV41- */
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u32 addr = nvkm_rd32(device, 0x009084);
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u32 data = nvkm_rd32(device, 0x009088);
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nv_error(bus, "MMIO %s of 0x%08x FAULT at 0x%06x\n",
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(addr & 0x00000002) ? "write" : "read", data,
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(addr & 0x00fffffc));
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nvkm_error(subdev, "MMIO %s of %08x FAULT at %06x\n",
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(addr & 0x00000002) ? "write" : "read", data,
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(addr & 0x00fffffc));
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stat &= ~0x00000008;
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nvkm_wr32(device, 0x001100, 0x00000008);
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}
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if (stat & 0x00070000) {
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subdev = nvkm_subdev(bus, NVDEV_SUBDEV_THERM);
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if (subdev && subdev->intr)
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subdev->intr(subdev);
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struct nvkm_therm *therm = device->therm;
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if (therm && therm->subdev.intr)
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therm->subdev.intr(&therm->subdev);
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stat &= ~0x00070000;
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nvkm_wr32(device, 0x001100, 0x00070000);
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}
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if (stat) {
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nv_error(bus, "unknown intr 0x%08x\n", stat);
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nvkm_error(subdev, "intr %08x\n", stat);
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nvkm_mask(device, 0x001140, stat, 0x00000000);
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}
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}
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@ -24,6 +24,7 @@
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*/
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#include "nv04.h"
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#include <subdev/therm.h>
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#include <subdev/timer.h>
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static int
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@ -51,32 +52,31 @@ nv50_bus_hwsq_exec(struct nvkm_bus *bus, u32 *data, u32 size)
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void
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nv50_bus_intr(struct nvkm_subdev *subdev)
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{
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struct nvkm_bus *bus = nvkm_bus(subdev);
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struct nvkm_device *device = bus->subdev.device;
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struct nvkm_device *device = subdev->device;
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u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140);
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if (stat & 0x00000008) {
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u32 addr = nvkm_rd32(device, 0x009084);
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u32 data = nvkm_rd32(device, 0x009088);
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nv_error(bus, "MMIO %s of 0x%08x FAULT at 0x%06x\n",
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(addr & 0x00000002) ? "write" : "read", data,
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(addr & 0x00fffffc));
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nvkm_error(subdev, "MMIO %s of %08x FAULT at %06x\n",
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(addr & 0x00000002) ? "write" : "read", data,
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(addr & 0x00fffffc));
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stat &= ~0x00000008;
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nvkm_wr32(device, 0x001100, 0x00000008);
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}
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if (stat & 0x00010000) {
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subdev = nvkm_subdev(bus, NVDEV_SUBDEV_THERM);
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if (subdev && subdev->intr)
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subdev->intr(subdev);
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struct nvkm_therm *therm = device->therm;
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if (therm && therm->subdev.intr)
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therm->subdev.intr(&therm->subdev);
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stat &= ~0x00010000;
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nvkm_wr32(device, 0x001100, 0x00010000);
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}
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if (stat) {
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nv_error(bus, "unknown intr 0x%08x\n", stat);
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nvkm_error(subdev, "intr %08x\n", stat);
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nvkm_mask(device, 0x001140, stat, 0);
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}
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}
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