arm64: dts: renesas: r8a77965: Use r8a77965-cpg-mssr binding definitions
Replace the hardcoded clock indices by R8A77965_CLK_* symbols. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -737,7 +737,7 @@
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reg = <0 0xe6e60000 0 64>;
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 207>,
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<&cpg CPG_CORE 20>,
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<&cpg CPG_CORE R8A77965_CLK_S3D1>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x51>, <&dmac1 0x50>,
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@ -754,7 +754,7 @@
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reg = <0 0xe6e68000 0 64>;
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 206>,
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<&cpg CPG_CORE 20>,
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<&cpg CPG_CORE R8A77965_CLK_S3D1>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x53>, <&dmac1 0x52>,
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@ -771,7 +771,7 @@
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reg = <0 0xe6e88000 0 64>;
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interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 310>,
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<&cpg CPG_CORE 20>,
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<&cpg CPG_CORE R8A77965_CLK_S3D1>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
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@ -785,7 +785,7 @@
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reg = <0 0xe6c50000 0 64>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 204>,
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<&cpg CPG_CORE 20>,
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<&cpg CPG_CORE R8A77965_CLK_S3D1>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac0 0x57>, <&dmac0 0x56>;
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@ -801,7 +801,7 @@
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reg = <0 0xe6c40000 0 64>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 203>,
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<&cpg CPG_CORE 20>,
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<&cpg CPG_CORE R8A77965_CLK_S3D1>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac0 0x59>, <&dmac0 0x58>;
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@ -817,7 +817,7 @@
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reg = <0 0xe6f30000 0 64>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 202>,
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<&cpg CPG_CORE 20>,
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<&cpg CPG_CORE R8A77965_CLK_S3D1>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
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