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sh_eth: add sh_eth_cpu_data::gecmr flag 

Not all Ether controllers having the Gigabit register layout have GECMR --
RZ/A1 (AKA R7S72100) actually has the same layout but no Gigabit speed
support and hence no GECMR. In the past, the new register map table was
added for this SoC, now I think we should have used the existing Gigabit
table with the differences (such as GECMR) covered by the mere flags in
the 'struct sh_eth_cpu_data'. Add such flag for GECMR -- and then we can
get rid of the R7S72100 specific layout in the next patch...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Tested-by: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sergei Shtylyov 2020-02-15 23:13:45 +03:00 committed by David S. Miller
parent 7bf47f609f
commit a6318d57f6
2 changed files with 14 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/net/ethernet/renesas/sh_eth.c
View File

@ -569,6 +569,9 @@ static void sh_eth_set_rate_gether(struct net_device *ndev)
{ {
struct sh_eth_private *mdp = netdev_priv(ndev); struct sh_eth_private *mdp = netdev_priv(ndev);
if (WARN_ON(!mdp->cd->gecmr))
return;
switch (mdp->speed) { switch (mdp->speed) {
case 10: /* 10BASE */ case 10: /* 10BASE */
sh_eth_write(ndev, GECMR_10, GECMR); sh_eth_write(ndev, GECMR_10, GECMR);
@ -663,6 +666,7 @@ static struct sh_eth_cpu_data r8a7740_data = {
.apr = 1, .apr = 1,
.mpr = 1, .mpr = 1,
.tpauser = 1, .tpauser = 1,
.gecmr = 1,
.bculr = 1, .bculr = 1,
.hw_swap = 1, .hw_swap = 1,
.rpadir = 1, .rpadir = 1,
@ -788,6 +792,7 @@ static struct sh_eth_cpu_data r8a77980_data = {
.apr = 1, .apr = 1,
.mpr = 1, .mpr = 1,
.tpauser = 1, .tpauser = 1,
.gecmr = 1,
.bculr = 1, .bculr = 1,
.hw_swap = 1, .hw_swap = 1,
.nbst = 1, .nbst = 1,
@ -957,6 +962,9 @@ static void sh_eth_set_rate_giga(struct net_device *ndev)
{ {
struct sh_eth_private *mdp = netdev_priv(ndev); struct sh_eth_private *mdp = netdev_priv(ndev);
if (WARN_ON(!mdp->cd->gecmr))
return;
switch (mdp->speed) { switch (mdp->speed) {
case 10: /* 10BASE */ case 10: /* 10BASE */
sh_eth_write(ndev, 0x00000000, GECMR); sh_eth_write(ndev, 0x00000000, GECMR);
@ -1002,6 +1010,7 @@ static struct sh_eth_cpu_data sh7757_data_giga = {
.apr = 1, .apr = 1,
.mpr = 1, .mpr = 1,
.tpauser = 1, .tpauser = 1,
.gecmr = 1,
.bculr = 1, .bculr = 1,
.hw_swap = 1, .hw_swap = 1,
.rpadir = 1, .rpadir = 1,
@ -1042,6 +1051,7 @@ static struct sh_eth_cpu_data sh7734_data = {
.apr = 1, .apr = 1,
.mpr = 1, .mpr = 1,
.tpauser = 1, .tpauser = 1,
.gecmr = 1,
.bculr = 1, .bculr = 1,
.hw_swap = 1, .hw_swap = 1,
.no_trimd = 1, .no_trimd = 1,
@ -1083,6 +1093,7 @@ static struct sh_eth_cpu_data sh7763_data = {
.apr = 1, .apr = 1,
.mpr = 1, .mpr = 1,
.tpauser = 1, .tpauser = 1,
.gecmr = 1,
.bculr = 1, .bculr = 1,
.hw_swap = 1, .hw_swap = 1,
.no_trimd = 1, .no_trimd = 1,
@ -2181,6 +2192,7 @@ static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
if (cd->tpauser) if (cd->tpauser)
add_reg(TPAUSER); add_reg(TPAUSER);
add_reg(TPAUSECR); add_reg(TPAUSECR);
if (cd->gecmr)
add_reg(GECMR); add_reg(GECMR);
if (cd->bculr) if (cd->bculr)
add_reg(BCULR); add_reg(BCULR);

1
drivers/net/ethernet/renesas/sh_eth.h
View File

@ -490,6 +490,7 @@ struct sh_eth_cpu_data {
unsigned apr:1; /* EtherC has APR */ unsigned apr:1; /* EtherC has APR */
unsigned mpr:1; /* EtherC has MPR */ unsigned mpr:1; /* EtherC has MPR */
unsigned tpauser:1; /* EtherC has TPAUSER */ unsigned tpauser:1; /* EtherC has TPAUSER */
unsigned gecmr:1; /* EtherC has GECMR */
unsigned bculr:1; /* EtherC has BCULR */ unsigned bculr:1; /* EtherC has BCULR */
unsigned tsu:1; /* EtherC has TSU */ unsigned tsu:1; /* EtherC has TSU */
unsigned hw_swap:1; /* E-DMAC has DE bit in EDMR */ unsigned hw_swap:1; /* E-DMAC has DE bit in EDMR */