qlge: Add ethtool register dump function.
Signed-off-by: Ron Mercer <ron.mercer@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Ron Mercer
David S. Miller
parent
bc083ce98e
commit
a61f802613
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@ -1400,6 +1400,153 @@ struct nic_stats {
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u64 rx_nic_fifo_drop;
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};
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/* Address/Length pairs for the coredump. */
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enum {
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MPI_CORE_REGS_ADDR = 0x00030000,
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MPI_CORE_REGS_CNT = 127,
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MPI_CORE_SH_REGS_CNT = 16,
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TEST_REGS_ADDR = 0x00001000,
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TEST_REGS_CNT = 23,
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RMII_REGS_ADDR = 0x00001040,
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RMII_REGS_CNT = 64,
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FCMAC1_REGS_ADDR = 0x00001080,
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FCMAC2_REGS_ADDR = 0x000010c0,
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FCMAC_REGS_CNT = 64,
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FC1_MBX_REGS_ADDR = 0x00001100,
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FC2_MBX_REGS_ADDR = 0x00001240,
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FC_MBX_REGS_CNT = 64,
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IDE_REGS_ADDR = 0x00001140,
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IDE_REGS_CNT = 64,
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NIC1_MBX_REGS_ADDR = 0x00001180,
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NIC2_MBX_REGS_ADDR = 0x00001280,
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NIC_MBX_REGS_CNT = 64,
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SMBUS_REGS_ADDR = 0x00001200,
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SMBUS_REGS_CNT = 64,
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I2C_REGS_ADDR = 0x00001fc0,
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I2C_REGS_CNT = 64,
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MEMC_REGS_ADDR = 0x00003000,
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MEMC_REGS_CNT = 256,
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PBUS_REGS_ADDR = 0x00007c00,
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PBUS_REGS_CNT = 256,
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MDE_REGS_ADDR = 0x00010000,
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MDE_REGS_CNT = 6,
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CODE_RAM_ADDR = 0x00020000,
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CODE_RAM_CNT = 0x2000,
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MEMC_RAM_ADDR = 0x00100000,
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MEMC_RAM_CNT = 0x2000,
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};
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#define MPI_COREDUMP_COOKIE 0x5555aaaa
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struct mpi_coredump_global_header {
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u32 cookie;
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u8 idString[16];
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u32 timeLo;
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u32 timeHi;
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u32 imageSize;
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u32 headerSize;
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u8 info[220];
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};
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struct mpi_coredump_segment_header {
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u32 cookie;
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u32 segNum;
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u32 segSize;
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u32 extra;
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u8 description[16];
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};
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/* Reg dump segment numbers. */
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enum {
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CORE_SEG_NUM = 1,
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TEST_LOGIC_SEG_NUM = 2,
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RMII_SEG_NUM = 3,
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FCMAC1_SEG_NUM = 4,
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FCMAC2_SEG_NUM = 5,
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FC1_MBOX_SEG_NUM = 6,
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IDE_SEG_NUM = 7,
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NIC1_MBOX_SEG_NUM = 8,
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SMBUS_SEG_NUM = 9,
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FC2_MBOX_SEG_NUM = 10,
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NIC2_MBOX_SEG_NUM = 11,
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I2C_SEG_NUM = 12,
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MEMC_SEG_NUM = 13,
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PBUS_SEG_NUM = 14,
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MDE_SEG_NUM = 15,
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NIC1_CONTROL_SEG_NUM = 16,
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NIC2_CONTROL_SEG_NUM = 17,
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NIC1_XGMAC_SEG_NUM = 18,
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NIC2_XGMAC_SEG_NUM = 19,
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WCS_RAM_SEG_NUM = 20,
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MEMC_RAM_SEG_NUM = 21,
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XAUI_AN_SEG_NUM = 22,
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XAUI_HSS_PCS_SEG_NUM = 23,
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XFI_AN_SEG_NUM = 24,
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XFI_TRAIN_SEG_NUM = 25,
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XFI_HSS_PCS_SEG_NUM = 26,
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XFI_HSS_TX_SEG_NUM = 27,
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XFI_HSS_RX_SEG_NUM = 28,
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XFI_HSS_PLL_SEG_NUM = 29,
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MISC_NIC_INFO_SEG_NUM = 30,
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INTR_STATES_SEG_NUM = 31,
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CAM_ENTRIES_SEG_NUM = 32,
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ROUTING_WORDS_SEG_NUM = 33,
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ETS_SEG_NUM = 34,
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PROBE_DUMP_SEG_NUM = 35,
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ROUTING_INDEX_SEG_NUM = 36,
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MAC_PROTOCOL_SEG_NUM = 37,
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XAUI2_AN_SEG_NUM = 38,
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XAUI2_HSS_PCS_SEG_NUM = 39,
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XFI2_AN_SEG_NUM = 40,
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XFI2_TRAIN_SEG_NUM = 41,
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XFI2_HSS_PCS_SEG_NUM = 42,
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XFI2_HSS_TX_SEG_NUM = 43,
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XFI2_HSS_RX_SEG_NUM = 44,
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XFI2_HSS_PLL_SEG_NUM = 45,
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SEM_REGS_SEG_NUM = 50
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};
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struct ql_nic_misc {
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u32 rx_ring_count;
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u32 tx_ring_count;
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u32 intr_count;
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u32 function;
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};
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struct ql_reg_dump {
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/* segment 0 */
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struct mpi_coredump_global_header mpi_global_header;
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/* segment 16 */
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struct mpi_coredump_segment_header nic_regs_seg_hdr;
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u32 nic_regs[64];
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/* segment 30 */
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struct mpi_coredump_segment_header misc_nic_seg_hdr;
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struct ql_nic_misc misc_nic_info;
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/* segment 31 */
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/* one interrupt state for each CQ */
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struct mpi_coredump_segment_header intr_states_seg_hdr;
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u32 intr_states[MAX_CPUS];
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/* segment 32 */
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/* 3 cam words each for 16 unicast,
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* 2 cam words for each of 32 multicast.
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*/
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struct mpi_coredump_segment_header cam_entries_seg_hdr;
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u32 cam_entries[(16 * 3) + (32 * 3)];
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/* segment 33 */
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struct mpi_coredump_segment_header nic_routing_words_seg_hdr;
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u32 nic_routing_words[16];
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/* segment 34 */
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struct mpi_coredump_segment_header ets_seg_hdr;
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u32 ets[8+2];
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};
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/*
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* intr_context structure is used during initialization
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* to hook the interrupts. It is also used in a single
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@ -1658,6 +1805,8 @@ int ql_mb_set_mgmnt_traffic_ctl(struct ql_adapter *qdev, u32 control);
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int ql_mb_get_port_cfg(struct ql_adapter *qdev);
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int ql_mb_set_port_cfg(struct ql_adapter *qdev);
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int ql_wait_fifo_empty(struct ql_adapter *qdev);
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void ql_gen_reg_dump(struct ql_adapter *qdev,
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struct ql_reg_dump *mpi_coredump);
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#if 1
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#define QL_ALL_DUMP
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@ -1,5 +1,185 @@
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#include "qlge.h"
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static int ql_get_ets_regs(struct ql_adapter *qdev, u32 * buf)
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{
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int status = 0;
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int i;
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for (i = 0; i < 8; i++, buf++) {
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ql_write32(qdev, NIC_ETS, i << 29 | 0x08000000);
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*buf = ql_read32(qdev, NIC_ETS);
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}
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for (i = 0; i < 2; i++, buf++) {
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ql_write32(qdev, CNA_ETS, i << 29 | 0x08000000);
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*buf = ql_read32(qdev, CNA_ETS);
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}
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return status;
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}
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static void ql_get_intr_states(struct ql_adapter *qdev, u32 * buf)
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{
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int i;
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for (i = 0; i < qdev->rx_ring_count; i++, buf++) {
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ql_write32(qdev, INTR_EN,
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qdev->intr_context[i].intr_read_mask);
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*buf = ql_read32(qdev, INTR_EN);
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}
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}
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static int ql_get_cam_entries(struct ql_adapter *qdev, u32 * buf)
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{
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int i, status;
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u32 value[3];
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status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
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if (status)
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return status;
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for (i = 0; i < 16; i++) {
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status = ql_get_mac_addr_reg(qdev,
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MAC_ADDR_TYPE_CAM_MAC, i, value);
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if (status) {
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QPRINTK(qdev, DRV, ERR,
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"Failed read of mac index register.\n");
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goto err;
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}
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*buf++ = value[0]; /* lower MAC address */
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*buf++ = value[1]; /* upper MAC address */
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*buf++ = value[2]; /* output */
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}
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for (i = 0; i < 32; i++) {
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status = ql_get_mac_addr_reg(qdev,
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MAC_ADDR_TYPE_MULTI_MAC, i, value);
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if (status) {
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QPRINTK(qdev, DRV, ERR,
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"Failed read of mac index register.\n");
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goto err;
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}
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*buf++ = value[0]; /* lower Mcast address */
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*buf++ = value[1]; /* upper Mcast address */
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}
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err:
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ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
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return status;
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}
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static int ql_get_routing_entries(struct ql_adapter *qdev, u32 * buf)
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{
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int status;
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u32 value, i;
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status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
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if (status)
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return status;
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for (i = 0; i < 16; i++) {
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status = ql_get_routing_reg(qdev, i, &value);
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if (status) {
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QPRINTK(qdev, DRV, ERR,
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"Failed read of routing index register.\n");
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goto err;
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} else {
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*buf++ = value;
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}
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}
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err:
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ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
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return status;
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}
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/* Create a coredump segment header */
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static void ql_build_coredump_seg_header(
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struct mpi_coredump_segment_header *seg_hdr,
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u32 seg_number, u32 seg_size, u8 *desc)
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{
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memset(seg_hdr, 0, sizeof(struct mpi_coredump_segment_header));
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seg_hdr->cookie = MPI_COREDUMP_COOKIE;
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seg_hdr->segNum = seg_number;
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seg_hdr->segSize = seg_size;
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memcpy(seg_hdr->description, desc, (sizeof(seg_hdr->description)) - 1);
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}
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void ql_gen_reg_dump(struct ql_adapter *qdev,
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struct ql_reg_dump *mpi_coredump)
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{
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int i, status;
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memset(&(mpi_coredump->mpi_global_header), 0,
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sizeof(struct mpi_coredump_global_header));
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mpi_coredump->mpi_global_header.cookie = MPI_COREDUMP_COOKIE;
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mpi_coredump->mpi_global_header.headerSize =
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sizeof(struct mpi_coredump_global_header);
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mpi_coredump->mpi_global_header.imageSize =
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sizeof(struct ql_reg_dump);
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memcpy(mpi_coredump->mpi_global_header.idString, "MPI Coredump",
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sizeof(mpi_coredump->mpi_global_header.idString));
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/* segment 16 */
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ql_build_coredump_seg_header(&mpi_coredump->misc_nic_seg_hdr,
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MISC_NIC_INFO_SEG_NUM,
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sizeof(struct mpi_coredump_segment_header)
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+ sizeof(mpi_coredump->misc_nic_info),
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"MISC NIC INFO");
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mpi_coredump->misc_nic_info.rx_ring_count = qdev->rx_ring_count;
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mpi_coredump->misc_nic_info.tx_ring_count = qdev->tx_ring_count;
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mpi_coredump->misc_nic_info.intr_count = qdev->intr_count;
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mpi_coredump->misc_nic_info.function = qdev->func;
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/* Segment 16, Rev C. Step 18 */
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ql_build_coredump_seg_header(&mpi_coredump->nic_regs_seg_hdr,
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NIC1_CONTROL_SEG_NUM,
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sizeof(struct mpi_coredump_segment_header)
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+ sizeof(mpi_coredump->nic_regs),
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"NIC Registers");
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/* Get generic reg dump */
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for (i = 0; i < 64; i++)
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mpi_coredump->nic_regs[i] = ql_read32(qdev, i * sizeof(u32));
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/* Segment 31 */
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/* Get indexed register values. */
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ql_build_coredump_seg_header(&mpi_coredump->intr_states_seg_hdr,
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INTR_STATES_SEG_NUM,
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sizeof(struct mpi_coredump_segment_header)
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+ sizeof(mpi_coredump->intr_states),
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"INTR States");
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ql_get_intr_states(qdev, &mpi_coredump->intr_states[0]);
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ql_build_coredump_seg_header(&mpi_coredump->cam_entries_seg_hdr,
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CAM_ENTRIES_SEG_NUM,
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sizeof(struct mpi_coredump_segment_header)
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+ sizeof(mpi_coredump->cam_entries),
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"CAM Entries");
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status = ql_get_cam_entries(qdev, &mpi_coredump->cam_entries[0]);
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if (status)
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return;
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ql_build_coredump_seg_header(&mpi_coredump->nic_routing_words_seg_hdr,
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ROUTING_WORDS_SEG_NUM,
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sizeof(struct mpi_coredump_segment_header)
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+ sizeof(mpi_coredump->nic_routing_words),
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"Routing Words");
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status = ql_get_routing_entries(qdev,
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&mpi_coredump->nic_routing_words[0]);
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if (status)
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return;
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/* Segment 34 (Rev C. step 23) */
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ql_build_coredump_seg_header(&mpi_coredump->ets_seg_hdr,
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ETS_SEG_NUM,
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sizeof(struct mpi_coredump_segment_header)
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+ sizeof(mpi_coredump->ets),
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"ETS Registers");
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status = ql_get_ets_regs(qdev, &mpi_coredump->ets[0]);
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if (status)
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return;
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}
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#ifdef QL_REG_DUMP
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static void ql_dump_intr_states(struct ql_adapter *qdev)
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{
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@ -428,6 +428,20 @@ static int ql_phys_id(struct net_device *ndev, u32 data)
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return 0;
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}
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static int ql_get_regs_len(struct net_device *ndev)
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{
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return sizeof(struct ql_reg_dump);
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}
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static void ql_get_regs(struct net_device *ndev,
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struct ethtool_regs *regs, void *p)
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{
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struct ql_adapter *qdev = netdev_priv(ndev);
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ql_gen_reg_dump(qdev, p);
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}
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static int ql_get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
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{
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struct ql_adapter *qdev = netdev_priv(dev);
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@ -555,6 +569,8 @@ const struct ethtool_ops qlge_ethtool_ops = {
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.get_drvinfo = ql_get_drvinfo,
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.get_wol = ql_get_wol,
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.set_wol = ql_set_wol,
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.get_regs_len = ql_get_regs_len,
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.get_regs = ql_get_regs,
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.get_msglevel = ql_get_msglevel,
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.set_msglevel = ql_set_msglevel,
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.get_link = ethtool_op_get_link,
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