Merge branch 'lee-fixes' into devel
This commit is contained in:
Linus Walleij
commit
a6175e894d
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@ -24,6 +24,7 @@
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* @interrupt_trigger : specifies the hardware configured IRQ trigger type
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* (rising, falling, both, high)
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* @mapped_irq : kernel mapped irq number.
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* @irq_chip : IRQ chip configuration
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*/
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struct altera_gpio_chip {
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struct of_mm_gpio_chip mmchip;
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@ -69,7 +70,7 @@ static void altera_gpio_irq_mask(struct irq_data *d)
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raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
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}
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/**
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/*
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* This controller's IRQ type is synthesized in hardware, so this function
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* just checks if the requested set_type matches the synthesized IRQ type
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*/
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@ -47,13 +47,13 @@
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/**
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* struct it87_gpio - it87-specific GPIO chip
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* @chip the underlying gpio_chip structure
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* @lock a lock to avoid races between operations
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* @io_base base address for gpio ports
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* @io_size size of the port rage starting from io_base.
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* @output_base Super I/O register address for Output Enable register
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* @simple_base Super I/O 'Simple I/O' Enable register
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* @simple_size Super IO 'Simple I/O' Enable register size; this is
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* @chip: the underlying gpio_chip structure
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* @lock: a lock to avoid races between operations
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* @io_base: base address for gpio ports
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* @io_size: size of the port rage starting from io_base.
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* @output_base: Super I/O register address for Output Enable register
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* @simple_base: Super I/O 'Simple I/O' Enable register
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* @simple_size: Super IO 'Simple I/O' Enable register size; this is
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* required because IT87xx chips might only provide Simple I/O
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* switches on a subset of lines, whereas the others keep the
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* same status all time.
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@ -127,7 +127,7 @@ static int mlxbf_gpio_resume(struct platform_device *pdev)
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}
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#endif
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static const struct acpi_device_id mlxbf_gpio_acpi_match[] = {
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static const struct acpi_device_id __maybe_unused mlxbf_gpio_acpi_match[] = {
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{ "MLNXBF02", 0 },
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{}
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};
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@ -149,6 +149,8 @@ static int mlxbf2_gpio_lock_acquire(struct mlxbf2_gpio_context *gs)
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* Release the YU arm_gpio_lock after changing the direction mode.
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*/
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static void mlxbf2_gpio_lock_release(struct mlxbf2_gpio_context *gs)
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__releases(&gs->gc.bgpio_lock)
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__releases(yu_arm_gpio_lock_param.lock)
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{
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writel(YU_ARM_GPIO_LOCK_RELEASE, yu_arm_gpio_lock_param.io);
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spin_unlock(&gs->gc.bgpio_lock);
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@ -309,7 +311,7 @@ static int mlxbf2_gpio_resume(struct platform_device *pdev)
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}
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#endif
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static const struct acpi_device_id mlxbf2_gpio_acpi_match[] = {
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static const struct acpi_device_id __maybe_unused mlxbf2_gpio_acpi_match[] = {
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{ "MLNXBF22", 0 },
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{},
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};
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@ -48,7 +48,7 @@ enum {
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* struct sprd_pmic_eic - PMIC EIC controller
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* @chip: the gpio_chip structure.
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* @intc: the irq_chip structure.
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* @regmap: the regmap from the parent device.
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* @map: the regmap from the parent device.
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* @offset: the EIC controller's offset address of the PMIC.
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* @reg: the array to cache the EIC registers.
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* @buslock: for bus lock/sync and unlock.
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@ -49,7 +49,7 @@ struct sama5d2_piobu {
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struct regmap *regmap;
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};
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/**
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/*
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* sama5d2_piobu_setup_pin() - prepares a pin for set_direction call
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*
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* Do not consider pin for tamper detection (normal and backup modes)
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@ -73,7 +73,7 @@ static int sama5d2_piobu_setup_pin(struct gpio_chip *chip, unsigned int pin)
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return regmap_update_bits(piobu->regmap, PIOBU_WKPR, mask, 0);
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}
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/**
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/*
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* sama5d2_piobu_write_value() - writes value & mask at the pin's PIOBU register
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*/
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static int sama5d2_piobu_write_value(struct gpio_chip *chip, unsigned int pin,
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@ -88,7 +88,7 @@ static int sama5d2_piobu_write_value(struct gpio_chip *chip, unsigned int pin,
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return regmap_update_bits(piobu->regmap, reg, mask, value);
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}
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/**
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/*
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* sama5d2_piobu_read_value() - read the value with masking from the pin's PIOBU
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* register
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*/
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@ -108,7 +108,7 @@ static int sama5d2_piobu_read_value(struct gpio_chip *chip, unsigned int pin,
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return val & mask;
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}
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/**
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/*
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* sama5d2_piobu_get_direction() - gpiochip get_direction
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*/
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static int sama5d2_piobu_get_direction(struct gpio_chip *chip,
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@ -123,7 +123,7 @@ static int sama5d2_piobu_get_direction(struct gpio_chip *chip,
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GPIO_LINE_DIRECTION_OUT;
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}
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/**
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/*
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* sama5d2_piobu_direction_input() - gpiochip direction_input
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*/
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static int sama5d2_piobu_direction_input(struct gpio_chip *chip,
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@ -132,7 +132,7 @@ static int sama5d2_piobu_direction_input(struct gpio_chip *chip,
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return sama5d2_piobu_write_value(chip, pin, PIOBU_DIRECTION, PIOBU_IN);
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}
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/**
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/*
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* sama5d2_piobu_direction_output() - gpiochip direction_output
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*/
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static int sama5d2_piobu_direction_output(struct gpio_chip *chip,
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@ -147,7 +147,7 @@ static int sama5d2_piobu_direction_output(struct gpio_chip *chip,
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val);
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}
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/**
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/*
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* sama5d2_piobu_get() - gpiochip get
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*/
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static int sama5d2_piobu_get(struct gpio_chip *chip, unsigned int pin)
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@ -166,7 +166,7 @@ static int sama5d2_piobu_get(struct gpio_chip *chip, unsigned int pin)
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return !!ret;
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}
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/**
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/*
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* sama5d2_piobu_set() - gpiochip set
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*/
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static void sama5d2_piobu_set(struct gpio_chip *chip, unsigned int pin,
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@ -24,16 +24,16 @@
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/**
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* struct syscon_gpio_data - Configuration for the device.
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* compatible: SYSCON driver compatible string.
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* flags: Set of GPIO_SYSCON_FEAT_ flags:
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* @compatible: SYSCON driver compatible string.
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* @flags: Set of GPIO_SYSCON_FEAT_ flags:
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* GPIO_SYSCON_FEAT_IN: GPIOs supports input,
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* GPIO_SYSCON_FEAT_OUT: GPIOs supports output,
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* GPIO_SYSCON_FEAT_DIR: GPIOs supports switch direction.
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* bit_count: Number of bits used as GPIOs.
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* dat_bit_offset: Offset (in bits) to the first GPIO bit.
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* dir_bit_offset: Optional offset (in bits) to the first bit to switch
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* @bit_count: Number of bits used as GPIOs.
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* @dat_bit_offset: Offset (in bits) to the first GPIO bit.
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* @dir_bit_offset: Optional offset (in bits) to the first bit to switch
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* GPIO direction (Used with GPIO_SYSCON_FEAT_DIR flag).
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* set: HW specific callback to assigns output value
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* @set: HW specific callback to assigns output value
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* for signal "offset"
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*/
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@ -25,6 +25,9 @@
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/**
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* of_gpio_spi_cs_get_count() - special GPIO counting for SPI
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* @dev: Consuming device
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* @con_id: Function within the GPIO consumer
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*
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* Some elder GPIO controllers need special quirks. Currently we handle
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* the Freescale GPIO controller with bindings that doesn't use the
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* established "cs-gpios" for chip selects but instead rely on
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