drm/amd/pm: enable deep sleep features control for SMU 13.0.0
Fulfill the interface for deep sleep features control. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -275,5 +275,8 @@ int smu_v13_0_init_pptable_microcode(struct smu_context *smu);
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int smu_v13_0_run_btc(struct smu_context *smu);
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int smu_v13_0_deep_sleep_control(struct smu_context *smu,
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bool enablement);
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#endif
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#endif
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@ -2111,3 +2111,76 @@ int smu_v13_0_run_btc(struct smu_context *smu)
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return res;
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}
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int smu_v13_0_deep_sleep_control(struct smu_context *smu,
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bool enablement)
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{
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struct amdgpu_device *adev = smu->adev;
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int ret = 0;
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if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
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ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
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if (ret) {
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dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
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return ret;
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}
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}
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if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
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ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
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if (ret) {
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dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
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return ret;
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}
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}
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if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
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ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
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if (ret) {
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dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
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return ret;
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}
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}
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if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
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ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
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if (ret) {
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dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
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return ret;
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}
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}
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if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
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ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
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if (ret) {
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dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
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return ret;
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}
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}
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if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
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ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
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if (ret) {
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dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
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return ret;
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}
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}
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if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
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ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
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if (ret) {
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dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
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return ret;
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}
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}
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if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
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ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
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if (ret) {
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dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
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return ret;
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}
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}
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return ret;
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}
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@ -141,6 +141,14 @@ static struct cmn2asic_mapping smu_v13_0_0_feature_mask_map[SMU_FEATURE_COUNT] =
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[SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
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[SMU_FEATURE_FAN_CONTROL_BIT] = {1, FEATURE_FAN_CONTROL_BIT},
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[SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT},
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[SMU_FEATURE_DS_GFXCLK_BIT] = {1, FEATURE_DS_GFXCLK_BIT},
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[SMU_FEATURE_DS_SOCCLK_BIT] = {1, FEATURE_DS_SOCCLK_BIT},
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[SMU_FEATURE_DS_UCLK_BIT] = {1, FEATURE_DS_UCLK_BIT},
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[SMU_FEATURE_DS_FCLK_BIT] = {1, FEATURE_DS_FCLK_BIT},
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[SMU_FEATURE_DS_LCLK_BIT] = {1, FEATURE_DS_LCLK_BIT},
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[SMU_FEATURE_DS_VCN_BIT] = {1, FEATURE_DS_VCN_BIT},
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[SMU_FEATURE_DS_MP0CLK_BIT] = {1, FEATURE_SOC_MPCLK_DS_BIT},
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[SMU_FEATURE_DS_MP1CLK_BIT] = {1, FEATURE_BACO_MPCLK_DS_BIT},
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};
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static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = {
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@ -1571,6 +1579,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
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.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
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.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
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.set_tool_table_location = smu_v13_0_set_tool_table_location,
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.deep_sleep_control = smu_v13_0_deep_sleep_control,
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};
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void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
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