dt-bindings: clock: Add Qcom SM6125 GPUCC

Add device tree bindings for graphics clock controller for Qualcomm
Technology Inc's SM6125 SoCs.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230208091340.124641-6-konrad.dybcio@linaro.org
This commit is contained in:
Konrad Dybcio 2023-02-08 10:13:35 +01:00 committed by Bjorn Andersson
parent fe15c26ee2
commit a5b9c5c548
2 changed files with 95 additions and 0 deletions

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm6125-gpucc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller on SM6125
maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
description: |
Qualcomm graphics clock control module provides clocks and power domains on
Qualcomm SoCs.
See also:: include/dt-bindings/clock/qcom,sm6125-gpucc.h
properties:
compatible:
enum:
- qcom,sm6125-gpucc
clocks:
items:
- description: Board XO source
- description: GPLL0 main branch source
'#clock-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm6125.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
soc {
#address-cells = <1>;
#size-cells = <1>;
clock-controller@5990000 {
compatible = "qcom,sm6125-gpucc";
reg = <0x05990000 0x9000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>;
#clock-cells = <1>;
#power-domain-cells = <1>;
};
};
...

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6125_H
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6125_H
/* Clocks */
#define GPU_CC_PLL0_OUT_AUX2 0
#define GPU_CC_PLL1_OUT_AUX2 1
#define GPU_CC_CRC_AHB_CLK 2
#define GPU_CC_CX_APB_CLK 3
#define GPU_CC_CX_GFX3D_CLK 4
#define GPU_CC_CX_GMU_CLK 5
#define GPU_CC_CX_SNOC_DVM_CLK 6
#define GPU_CC_CXO_AON_CLK 7
#define GPU_CC_CXO_CLK 8
#define GPU_CC_GMU_CLK_SRC 9
#define GPU_CC_SLEEP_CLK 10
#define GPU_CC_GX_GFX3D_CLK 11
#define GPU_CC_GX_GFX3D_CLK_SRC 12
#define GPU_CC_AHB_CLK 13
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14
/* GDSCs */
#define GPU_CX_GDSC 0
#define GPU_GX_GDSC 1
#endif