hwrng: cctrng - introduce Arm CryptoCell driver
Introduce low level Arm CryptoCell TRNG HW support. Signed-off-by: Hadar Gat <hadar.gat@arm.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Hadar Gat
Herbert Xu
parent
ffb57daad3
commit
a583ed310b
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@ -474,6 +474,18 @@ config HW_RANDOM_KEYSTONE
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help
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This option enables Keystone's hardware random generator.
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config HW_RANDOM_CCTRNG
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tristate "Arm CryptoCell True Random Number Generator support"
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default HW_RANDOM
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help
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This driver provides support for the True Random Number
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Generator available in Arm TrustZone CryptoCell.
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To compile this driver as a module, choose M here: the module
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will be called cctrng.
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If unsure, say Y.
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endif # HW_RANDOM
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config UML_RANDOM
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@ -41,3 +41,4 @@ obj-$(CONFIG_HW_RANDOM_S390) += s390-trng.o
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obj-$(CONFIG_HW_RANDOM_KEYSTONE) += ks-sa-rng.o
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obj-$(CONFIG_HW_RANDOM_OPTEE) += optee-rng.o
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obj-$(CONFIG_HW_RANDOM_NPCM) += npcm-rng.o
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obj-$(CONFIG_HW_RANDOM_CCTRNG) += cctrng.o
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@ -0,0 +1,736 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (C) 2019-2020 ARM Limited or its affiliates. */
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/hw_random.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/interrupt.h>
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#include <linux/irqreturn.h>
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#include <linux/workqueue.h>
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#include <linux/circ_buf.h>
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#include <linux/completion.h>
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#include <linux/of.h>
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#include <linux/bitfield.h>
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#include "cctrng.h"
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#define CC_REG_LOW(name) (name ## _BIT_SHIFT)
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#define CC_REG_HIGH(name) (CC_REG_LOW(name) + name ## _BIT_SIZE - 1)
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#define CC_GENMASK(name) GENMASK(CC_REG_HIGH(name), CC_REG_LOW(name))
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#define CC_REG_FLD_GET(reg_name, fld_name, reg_val) \
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(FIELD_GET(CC_GENMASK(CC_ ## reg_name ## _ ## fld_name), reg_val))
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#define CC_HW_RESET_LOOP_COUNT 10
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#define CC_TRNG_SUSPEND_TIMEOUT 3000
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/* data circular buffer in words must be:
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* - of a power-of-2 size (limitation of circ_buf.h macros)
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* - at least 6, the size generated in the EHR according to HW implementation
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*/
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#define CCTRNG_DATA_BUF_WORDS 32
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/* The timeout for the TRNG operation should be calculated with the formula:
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* Timeout = EHR_NUM * VN_COEFF * EHR_LENGTH * SAMPLE_CNT * SCALE_VALUE
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* while:
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* - SAMPLE_CNT is input value from the characterisation process
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* - all the rest are constants
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*/
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#define EHR_NUM 1
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#define VN_COEFF 4
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#define EHR_LENGTH CC_TRNG_EHR_IN_BITS
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#define SCALE_VALUE 2
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#define CCTRNG_TIMEOUT(smpl_cnt) \
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(EHR_NUM * VN_COEFF * EHR_LENGTH * smpl_cnt * SCALE_VALUE)
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struct cctrng_drvdata {
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struct platform_device *pdev;
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void __iomem *cc_base;
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struct clk *clk;
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struct hwrng rng;
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u32 active_rosc;
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/* Sampling interval for each ring oscillator:
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* count of ring oscillator cycles between consecutive bits sampling.
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* Value of 0 indicates non-valid rosc
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*/
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u32 smpl_ratio[CC_TRNG_NUM_OF_ROSCS];
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u32 data_buf[CCTRNG_DATA_BUF_WORDS];
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struct circ_buf circ;
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struct work_struct compwork;
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struct work_struct startwork;
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/* pending_hw - 1 when HW is pending, 0 when it is idle */
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atomic_t pending_hw;
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/* protects against multiple concurrent consumers of data_buf */
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spinlock_t read_lock;
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};
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/* functions for write/read CC registers */
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static inline void cc_iowrite(struct cctrng_drvdata *drvdata, u32 reg, u32 val)
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{
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iowrite32(val, (drvdata->cc_base + reg));
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}
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static inline u32 cc_ioread(struct cctrng_drvdata *drvdata, u32 reg)
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{
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return ioread32(drvdata->cc_base + reg);
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}
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static int cc_trng_pm_get(struct device *dev)
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{
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int rc = 0;
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rc = pm_runtime_get_sync(dev);
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/* pm_runtime_get_sync() can return 1 as a valid return code */
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return (rc == 1 ? 0 : rc);
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}
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static void cc_trng_pm_put_suspend(struct device *dev)
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{
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int rc = 0;
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pm_runtime_mark_last_busy(dev);
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rc = pm_runtime_put_autosuspend(dev);
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if (rc)
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dev_err(dev, "pm_runtime_put_autosuspend returned %x\n", rc);
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}
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static int cc_trng_pm_init(struct cctrng_drvdata *drvdata)
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{
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struct device *dev = &(drvdata->pdev->dev);
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/* must be before the enabling to avoid redundant suspending */
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pm_runtime_set_autosuspend_delay(dev, CC_TRNG_SUSPEND_TIMEOUT);
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pm_runtime_use_autosuspend(dev);
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/* set us as active - note we won't do PM ops until cc_trng_pm_go()! */
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return pm_runtime_set_active(dev);
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}
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static void cc_trng_pm_go(struct cctrng_drvdata *drvdata)
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{
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struct device *dev = &(drvdata->pdev->dev);
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/* enable the PM module*/
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pm_runtime_enable(dev);
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}
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static void cc_trng_pm_fini(struct cctrng_drvdata *drvdata)
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{
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struct device *dev = &(drvdata->pdev->dev);
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pm_runtime_disable(dev);
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}
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static inline int cc_trng_parse_sampling_ratio(struct cctrng_drvdata *drvdata)
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{
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struct device *dev = &(drvdata->pdev->dev);
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struct device_node *np = drvdata->pdev->dev.of_node;
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int rc;
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int i;
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/* ret will be set to 0 if at least one rosc has (sampling ratio > 0) */
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int ret = -EINVAL;
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rc = of_property_read_u32_array(np, "arm,rosc-ratio",
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drvdata->smpl_ratio,
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CC_TRNG_NUM_OF_ROSCS);
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if (rc) {
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/* arm,rosc-ratio was not found in device tree */
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return rc;
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}
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/* verify that at least one rosc has (sampling ratio > 0) */
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for (i = 0; i < CC_TRNG_NUM_OF_ROSCS; ++i) {
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dev_dbg(dev, "rosc %d sampling ratio %u",
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i, drvdata->smpl_ratio[i]);
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if (drvdata->smpl_ratio[i] > 0)
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ret = 0;
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}
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return ret;
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}
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static int cc_trng_change_rosc(struct cctrng_drvdata *drvdata)
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{
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struct device *dev = &(drvdata->pdev->dev);
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dev_dbg(dev, "cctrng change rosc (was %d)\n", drvdata->active_rosc);
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drvdata->active_rosc += 1;
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while (drvdata->active_rosc < CC_TRNG_NUM_OF_ROSCS) {
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if (drvdata->smpl_ratio[drvdata->active_rosc] > 0)
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return 0;
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drvdata->active_rosc += 1;
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}
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return -EINVAL;
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}
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static void cc_trng_enable_rnd_source(struct cctrng_drvdata *drvdata)
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{
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u32 max_cycles;
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/* Set watchdog threshold to maximal allowed time (in CPU cycles) */
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max_cycles = CCTRNG_TIMEOUT(drvdata->smpl_ratio[drvdata->active_rosc]);
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cc_iowrite(drvdata, CC_RNG_WATCHDOG_VAL_REG_OFFSET, max_cycles);
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/* enable the RND source */
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cc_iowrite(drvdata, CC_RND_SOURCE_ENABLE_REG_OFFSET, 0x1);
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/* unmask RNG interrupts */
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cc_iowrite(drvdata, CC_RNG_IMR_REG_OFFSET, (u32)~CC_RNG_INT_MASK);
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}
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/* increase circular data buffer index (head/tail) */
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static inline void circ_idx_inc(int *idx, int bytes)
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{
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*idx += (bytes + 3) >> 2;
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*idx &= (CCTRNG_DATA_BUF_WORDS - 1);
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}
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static inline size_t circ_buf_space(struct cctrng_drvdata *drvdata)
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{
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return CIRC_SPACE(drvdata->circ.head,
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drvdata->circ.tail, CCTRNG_DATA_BUF_WORDS);
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}
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static int cctrng_read(struct hwrng *rng, void *data, size_t max, bool wait)
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{
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/* current implementation ignores "wait" */
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struct cctrng_drvdata *drvdata = (struct cctrng_drvdata *)rng->priv;
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struct device *dev = &(drvdata->pdev->dev);
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u32 *buf = (u32 *)drvdata->circ.buf;
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size_t copied = 0;
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size_t cnt_w;
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size_t size;
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size_t left;
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if (!spin_trylock(&drvdata->read_lock)) {
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/* concurrent consumers from data_buf cannot be served */
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dev_dbg_ratelimited(dev, "unable to hold lock\n");
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return 0;
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}
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/* copy till end of data buffer (without wrap back) */
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cnt_w = CIRC_CNT_TO_END(drvdata->circ.head,
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drvdata->circ.tail, CCTRNG_DATA_BUF_WORDS);
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size = min((cnt_w<<2), max);
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memcpy(data, &(buf[drvdata->circ.tail]), size);
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copied = size;
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circ_idx_inc(&drvdata->circ.tail, size);
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/* copy rest of data in data buffer */
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left = max - copied;
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if (left > 0) {
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cnt_w = CIRC_CNT(drvdata->circ.head,
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drvdata->circ.tail, CCTRNG_DATA_BUF_WORDS);
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size = min((cnt_w<<2), left);
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memcpy(data, &(buf[drvdata->circ.tail]), size);
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copied += size;
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circ_idx_inc(&drvdata->circ.tail, size);
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}
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spin_unlock(&drvdata->read_lock);
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if (circ_buf_space(drvdata) >= CC_TRNG_EHR_IN_WORDS) {
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if (atomic_cmpxchg(&drvdata->pending_hw, 0, 1) == 0) {
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/* re-check space in buffer to avoid potential race */
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if (circ_buf_space(drvdata) >= CC_TRNG_EHR_IN_WORDS) {
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/* increment device's usage counter */
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int rc = cc_trng_pm_get(dev);
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if (rc) {
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dev_err(dev,
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"cc_trng_pm_get returned %x\n",
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rc);
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return rc;
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}
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/* schedule execution of deferred work handler
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* for filling of data buffer
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*/
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schedule_work(&drvdata->startwork);
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} else {
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atomic_set(&drvdata->pending_hw, 0);
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}
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}
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}
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return copied;
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}
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static void cc_trng_hw_trigger(struct cctrng_drvdata *drvdata)
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{
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u32 tmp_smpl_cnt = 0;
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struct device *dev = &(drvdata->pdev->dev);
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dev_dbg(dev, "cctrng hw trigger.\n");
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/* enable the HW RND clock */
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cc_iowrite(drvdata, CC_RNG_CLK_ENABLE_REG_OFFSET, 0x1);
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/* do software reset */
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cc_iowrite(drvdata, CC_RNG_SW_RESET_REG_OFFSET, 0x1);
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/* in order to verify that the reset has completed,
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* the sample count need to be verified
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*/
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do {
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/* enable the HW RND clock */
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cc_iowrite(drvdata, CC_RNG_CLK_ENABLE_REG_OFFSET, 0x1);
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/* set sampling ratio (rng_clocks) between consecutive bits */
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cc_iowrite(drvdata, CC_SAMPLE_CNT1_REG_OFFSET,
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drvdata->smpl_ratio[drvdata->active_rosc]);
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/* read the sampling ratio */
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tmp_smpl_cnt = cc_ioread(drvdata, CC_SAMPLE_CNT1_REG_OFFSET);
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} while (tmp_smpl_cnt != drvdata->smpl_ratio[drvdata->active_rosc]);
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/* disable the RND source for setting new parameters in HW */
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cc_iowrite(drvdata, CC_RND_SOURCE_ENABLE_REG_OFFSET, 0);
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cc_iowrite(drvdata, CC_RNG_ICR_REG_OFFSET, 0xFFFFFFFF);
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cc_iowrite(drvdata, CC_TRNG_CONFIG_REG_OFFSET, drvdata->active_rosc);
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/* Debug Control register: set to 0 - no bypasses */
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cc_iowrite(drvdata, CC_TRNG_DEBUG_CONTROL_REG_OFFSET, 0);
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cc_trng_enable_rnd_source(drvdata);
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}
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void cc_trng_compwork_handler(struct work_struct *w)
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{
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u32 isr = 0;
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u32 ehr_valid = 0;
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struct cctrng_drvdata *drvdata =
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container_of(w, struct cctrng_drvdata, compwork);
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struct device *dev = &(drvdata->pdev->dev);
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int i;
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/* stop DMA and the RNG source */
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cc_iowrite(drvdata, CC_RNG_DMA_ENABLE_REG_OFFSET, 0);
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cc_iowrite(drvdata, CC_RND_SOURCE_ENABLE_REG_OFFSET, 0);
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/* read RNG_ISR and check for errors */
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isr = cc_ioread(drvdata, CC_RNG_ISR_REG_OFFSET);
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ehr_valid = CC_REG_FLD_GET(RNG_ISR, EHR_VALID, isr);
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dev_dbg(dev, "Got RNG_ISR=0x%08X (EHR_VALID=%u)\n", isr, ehr_valid);
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#ifdef CONFIG_CRYPTO_FIPS
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if (CC_REG_FLD_GET(RNG_ISR, CRNGT_ERR, isr) && fips_enabled) {
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fips_fail_notify();
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/* FIPS error is fatal */
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panic("Got HW CRNGT error while fips is enabled!\n");
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}
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#endif
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/* Clear all pending RNG interrupts */
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cc_iowrite(drvdata, CC_RNG_ICR_REG_OFFSET, isr);
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if (!ehr_valid) {
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/* in case of AUTOCORR/TIMEOUT error, try the next ROSC */
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if (CC_REG_FLD_GET(RNG_ISR, AUTOCORR_ERR, isr) ||
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CC_REG_FLD_GET(RNG_ISR, WATCHDOG, isr)) {
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dev_dbg(dev, "cctrng autocorr/timeout error.\n");
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goto next_rosc;
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}
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/* in case of VN error, ignore it */
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}
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/* read EHR data from registers */
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for (i = 0; i < CC_TRNG_EHR_IN_WORDS; i++) {
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/* calc word ptr in data_buf */
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u32 *buf = (u32 *)drvdata->circ.buf;
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buf[drvdata->circ.head] = cc_ioread(drvdata,
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CC_EHR_DATA_0_REG_OFFSET + (i*sizeof(u32)));
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/* EHR_DATA registers are cleared on read. In case 0 value was
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* returned, restart the entropy collection.
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*/
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if (buf[drvdata->circ.head] == 0) {
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dev_dbg(dev, "Got 0 value in EHR. active_rosc %u\n",
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drvdata->active_rosc);
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goto next_rosc;
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}
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circ_idx_inc(&drvdata->circ.head, 1<<2);
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}
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atomic_set(&drvdata->pending_hw, 0);
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/* continue to fill data buffer if needed */
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if (circ_buf_space(drvdata) >= CC_TRNG_EHR_IN_WORDS) {
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if (atomic_cmpxchg(&drvdata->pending_hw, 0, 1) == 0) {
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/* Re-enable rnd source */
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cc_trng_enable_rnd_source(drvdata);
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return;
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}
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}
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cc_trng_pm_put_suspend(dev);
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dev_dbg(dev, "compwork handler done\n");
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return;
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next_rosc:
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if ((circ_buf_space(drvdata) >= CC_TRNG_EHR_IN_WORDS) &&
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(cc_trng_change_rosc(drvdata) == 0)) {
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/* trigger trng hw with next rosc */
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cc_trng_hw_trigger(drvdata);
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} else {
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atomic_set(&drvdata->pending_hw, 0);
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cc_trng_pm_put_suspend(dev);
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}
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}
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static irqreturn_t cc_isr(int irq, void *dev_id)
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{
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struct cctrng_drvdata *drvdata = (struct cctrng_drvdata *)dev_id;
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struct device *dev = &(drvdata->pdev->dev);
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u32 irr;
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/* if driver suspended return, probably shared interrupt */
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if (pm_runtime_suspended(dev))
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return IRQ_NONE;
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/* read the interrupt status */
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irr = cc_ioread(drvdata, CC_HOST_RGF_IRR_REG_OFFSET);
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dev_dbg(dev, "Got IRR=0x%08X\n", irr);
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if (irr == 0) /* Probably shared interrupt line */
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return IRQ_NONE;
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/* clear interrupt - must be before processing events */
|
||||
cc_iowrite(drvdata, CC_HOST_RGF_ICR_REG_OFFSET, irr);
|
||||
|
||||
/* RNG interrupt - most probable */
|
||||
if (irr & CC_HOST_RNG_IRQ_MASK) {
|
||||
/* Mask RNG interrupts - will be unmasked in deferred work */
|
||||
cc_iowrite(drvdata, CC_RNG_IMR_REG_OFFSET, 0xFFFFFFFF);
|
||||
|
||||
/* We clear RNG interrupt here,
|
||||
* to avoid it from firing as we'll unmask RNG interrupts.
|
||||
*/
|
||||
cc_iowrite(drvdata, CC_HOST_RGF_ICR_REG_OFFSET,
|
||||
CC_HOST_RNG_IRQ_MASK);
|
||||
|
||||
irr &= ~CC_HOST_RNG_IRQ_MASK;
|
||||
|
||||
/* schedule execution of deferred work handler */
|
||||
schedule_work(&drvdata->compwork);
|
||||
}
|
||||
|
||||
if (irr) {
|
||||
dev_dbg_ratelimited(dev,
|
||||
"IRR includes unknown cause bits (0x%08X)\n",
|
||||
irr);
|
||||
/* Just warning */
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
void cc_trng_startwork_handler(struct work_struct *w)
|
||||
{
|
||||
struct cctrng_drvdata *drvdata =
|
||||
container_of(w, struct cctrng_drvdata, startwork);
|
||||
|
||||
drvdata->active_rosc = 0;
|
||||
cc_trng_hw_trigger(drvdata);
|
||||
}
|
||||
|
||||
|
||||
static int cc_trng_clk_init(struct cctrng_drvdata *drvdata)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct device *dev = &(drvdata->pdev->dev);
|
||||
int rc = 0;
|
||||
|
||||
clk = devm_clk_get_optional(dev, NULL);
|
||||
if (IS_ERR(clk)) {
|
||||
if (PTR_ERR(clk) != -EPROBE_DEFER)
|
||||
dev_err(dev, "Error getting clock: %pe\n", clk);
|
||||
return PTR_ERR(clk);
|
||||
}
|
||||
drvdata->clk = clk;
|
||||
|
||||
rc = clk_prepare_enable(drvdata->clk);
|
||||
if (rc) {
|
||||
dev_err(dev, "Failed to enable clock\n");
|
||||
return rc;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void cc_trng_clk_fini(struct cctrng_drvdata *drvdata)
|
||||
{
|
||||
clk_disable_unprepare(drvdata->clk);
|
||||
}
|
||||
|
||||
|
||||
static int cctrng_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *req_mem_cc_regs = NULL;
|
||||
struct cctrng_drvdata *drvdata;
|
||||
struct device *dev = &pdev->dev;
|
||||
int rc = 0;
|
||||
u32 val;
|
||||
int irq;
|
||||
|
||||
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
|
||||
if (!drvdata)
|
||||
return -ENOMEM;
|
||||
|
||||
drvdata->rng.name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
|
||||
if (!drvdata->rng.name)
|
||||
return -ENOMEM;
|
||||
|
||||
drvdata->rng.read = cctrng_read;
|
||||
drvdata->rng.priv = (unsigned long)drvdata;
|
||||
drvdata->rng.quality = CC_TRNG_QUALITY;
|
||||
|
||||
platform_set_drvdata(pdev, drvdata);
|
||||
drvdata->pdev = pdev;
|
||||
|
||||
drvdata->circ.buf = (char *)drvdata->data_buf;
|
||||
|
||||
/* Get device resources */
|
||||
/* First CC registers space */
|
||||
req_mem_cc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
/* Map registers space */
|
||||
drvdata->cc_base = devm_ioremap_resource(dev, req_mem_cc_regs);
|
||||
if (IS_ERR(drvdata->cc_base)) {
|
||||
dev_err(dev, "Failed to ioremap registers");
|
||||
return PTR_ERR(drvdata->cc_base);
|
||||
}
|
||||
|
||||
dev_dbg(dev, "Got MEM resource (%s): %pR\n", req_mem_cc_regs->name,
|
||||
req_mem_cc_regs);
|
||||
dev_dbg(dev, "CC registers mapped from %pa to 0x%p\n",
|
||||
&req_mem_cc_regs->start, drvdata->cc_base);
|
||||
|
||||
/* Then IRQ */
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(dev, "Failed getting IRQ resource\n");
|
||||
return irq;
|
||||
}
|
||||
|
||||
/* parse sampling rate from device tree */
|
||||
rc = cc_trng_parse_sampling_ratio(drvdata);
|
||||
if (rc) {
|
||||
dev_err(dev, "Failed to get legal sampling ratio for rosc\n");
|
||||
return rc;
|
||||
}
|
||||
|
||||
rc = cc_trng_clk_init(drvdata);
|
||||
if (rc) {
|
||||
dev_err(dev, "cc_trng_clk_init failed\n");
|
||||
return rc;
|
||||
}
|
||||
|
||||
INIT_WORK(&drvdata->compwork, cc_trng_compwork_handler);
|
||||
INIT_WORK(&drvdata->startwork, cc_trng_startwork_handler);
|
||||
spin_lock_init(&drvdata->read_lock);
|
||||
|
||||
/* register the driver isr function */
|
||||
rc = devm_request_irq(dev, irq, cc_isr, IRQF_SHARED, "cctrng", drvdata);
|
||||
if (rc) {
|
||||
dev_err(dev, "Could not register to interrupt %d\n", irq);
|
||||
goto post_clk_err;
|
||||
}
|
||||
dev_dbg(dev, "Registered to IRQ: %d\n", irq);
|
||||
|
||||
/* Clear all pending interrupts */
|
||||
val = cc_ioread(drvdata, CC_HOST_RGF_IRR_REG_OFFSET);
|
||||
dev_dbg(dev, "IRR=0x%08X\n", val);
|
||||
cc_iowrite(drvdata, CC_HOST_RGF_ICR_REG_OFFSET, val);
|
||||
|
||||
/* unmask HOST RNG interrupt */
|
||||
cc_iowrite(drvdata, CC_HOST_RGF_IMR_REG_OFFSET,
|
||||
cc_ioread(drvdata, CC_HOST_RGF_IMR_REG_OFFSET) &
|
||||
~CC_HOST_RNG_IRQ_MASK);
|
||||
|
||||
/* init PM */
|
||||
rc = cc_trng_pm_init(drvdata);
|
||||
if (rc) {
|
||||
dev_err(dev, "cc_trng_pm_init failed\n");
|
||||
goto post_clk_err;
|
||||
}
|
||||
|
||||
/* increment device's usage counter */
|
||||
rc = cc_trng_pm_get(dev);
|
||||
if (rc) {
|
||||
dev_err(dev, "cc_trng_pm_get returned %x\n", rc);
|
||||
goto post_pm_err;
|
||||
}
|
||||
|
||||
/* set pending_hw to verify that HW won't be triggered from read */
|
||||
atomic_set(&drvdata->pending_hw, 1);
|
||||
|
||||
/* registration of the hwrng device */
|
||||
rc = hwrng_register(&drvdata->rng);
|
||||
if (rc) {
|
||||
dev_err(dev, "Could not register hwrng device.\n");
|
||||
goto post_pm_err;
|
||||
}
|
||||
|
||||
/* trigger HW to start generate data */
|
||||
drvdata->active_rosc = 0;
|
||||
cc_trng_hw_trigger(drvdata);
|
||||
|
||||
/* All set, we can allow auto-suspend */
|
||||
cc_trng_pm_go(drvdata);
|
||||
|
||||
dev_info(dev, "ARM cctrng device initialized\n");
|
||||
|
||||
return 0;
|
||||
|
||||
post_pm_err:
|
||||
cc_trng_pm_fini(drvdata);
|
||||
|
||||
post_clk_err:
|
||||
cc_trng_clk_fini(drvdata);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int cctrng_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct cctrng_drvdata *drvdata = platform_get_drvdata(pdev);
|
||||
struct device *dev = &pdev->dev;
|
||||
|
||||
dev_dbg(dev, "Releasing cctrng resources...\n");
|
||||
|
||||
hwrng_unregister(&drvdata->rng);
|
||||
|
||||
cc_trng_pm_fini(drvdata);
|
||||
|
||||
cc_trng_clk_fini(drvdata);
|
||||
|
||||
dev_info(dev, "ARM cctrng device terminated\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __maybe_unused cctrng_suspend(struct device *dev)
|
||||
{
|
||||
struct cctrng_drvdata *drvdata = dev_get_drvdata(dev);
|
||||
|
||||
dev_dbg(dev, "set HOST_POWER_DOWN_EN\n");
|
||||
cc_iowrite(drvdata, CC_HOST_POWER_DOWN_EN_REG_OFFSET,
|
||||
POWER_DOWN_ENABLE);
|
||||
|
||||
clk_disable_unprepare(drvdata->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool cctrng_wait_for_reset_completion(struct cctrng_drvdata *drvdata)
|
||||
{
|
||||
unsigned int val;
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < CC_HW_RESET_LOOP_COUNT; i++) {
|
||||
/* in cc7x3 NVM_IS_IDLE indicates that CC reset is
|
||||
* completed and device is fully functional
|
||||
*/
|
||||
val = cc_ioread(drvdata, CC_NVM_IS_IDLE_REG_OFFSET);
|
||||
if (val & BIT(CC_NVM_IS_IDLE_VALUE_BIT_SHIFT)) {
|
||||
/* hw indicate reset completed */
|
||||
return true;
|
||||
}
|
||||
/* allow scheduling other process on the processor */
|
||||
schedule();
|
||||
}
|
||||
/* reset not completed */
|
||||
return false;
|
||||
}
|
||||
|
||||
static int __maybe_unused cctrng_resume(struct device *dev)
|
||||
{
|
||||
struct cctrng_drvdata *drvdata = dev_get_drvdata(dev);
|
||||
int rc;
|
||||
|
||||
dev_dbg(dev, "unset HOST_POWER_DOWN_EN\n");
|
||||
/* Enables the device source clk */
|
||||
rc = clk_prepare_enable(drvdata->clk);
|
||||
if (rc) {
|
||||
dev_err(dev, "failed getting clock back on. We're toast.\n");
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* wait for Cryptocell reset completion */
|
||||
if (!cctrng_wait_for_reset_completion(drvdata)) {
|
||||
dev_err(dev, "Cryptocell reset not completed");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
/* unmask HOST RNG interrupt */
|
||||
cc_iowrite(drvdata, CC_HOST_RGF_IMR_REG_OFFSET,
|
||||
cc_ioread(drvdata, CC_HOST_RGF_IMR_REG_OFFSET) &
|
||||
~CC_HOST_RNG_IRQ_MASK);
|
||||
|
||||
cc_iowrite(drvdata, CC_HOST_POWER_DOWN_EN_REG_OFFSET,
|
||||
POWER_DOWN_DISABLE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static UNIVERSAL_DEV_PM_OPS(cctrng_pm, cctrng_suspend, cctrng_resume, NULL);
|
||||
|
||||
static const struct of_device_id arm_cctrng_dt_match[] = {
|
||||
{ .compatible = "arm,cryptocell-713-trng", },
|
||||
{ .compatible = "arm,cryptocell-703-trng", },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, arm_cctrng_dt_match);
|
||||
|
||||
static struct platform_driver cctrng_driver = {
|
||||
.driver = {
|
||||
.name = "cctrng",
|
||||
.of_match_table = arm_cctrng_dt_match,
|
||||
.pm = &cctrng_pm,
|
||||
},
|
||||
.probe = cctrng_probe,
|
||||
.remove = cctrng_remove,
|
||||
};
|
||||
|
||||
static int __init cctrng_mod_init(void)
|
||||
{
|
||||
/* Compile time assertion checks */
|
||||
BUILD_BUG_ON(CCTRNG_DATA_BUF_WORDS < 6);
|
||||
BUILD_BUG_ON((CCTRNG_DATA_BUF_WORDS & (CCTRNG_DATA_BUF_WORDS-1)) != 0);
|
||||
|
||||
return platform_driver_register(&cctrng_driver);
|
||||
}
|
||||
module_init(cctrng_mod_init);
|
||||
|
||||
static void __exit cctrng_mod_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&cctrng_driver);
|
||||
}
|
||||
module_exit(cctrng_mod_exit);
|
||||
|
||||
/* Module description */
|
||||
MODULE_DESCRIPTION("ARM CryptoCell TRNG Driver");
|
||||
MODULE_AUTHOR("ARM");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Copyright (C) 2019-2020 ARM Limited or its affiliates. */
|
||||
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#define POWER_DOWN_ENABLE 0x01
|
||||
#define POWER_DOWN_DISABLE 0x00
|
||||
|
||||
/* hwrng quality: bits of true entropy per 1024 bits of input */
|
||||
#define CC_TRNG_QUALITY 1024
|
||||
|
||||
/* CryptoCell TRNG HW definitions */
|
||||
#define CC_TRNG_NUM_OF_ROSCS 4
|
||||
/* The number of words generated in the entropy holding register (EHR)
|
||||
* 6 words (192 bit) according to HW implementation
|
||||
*/
|
||||
#define CC_TRNG_EHR_IN_WORDS 6
|
||||
#define CC_TRNG_EHR_IN_BITS (CC_TRNG_EHR_IN_WORDS * BITS_PER_TYPE(u32))
|
||||
|
||||
#define CC_HOST_RNG_IRQ_MASK BIT(CC_HOST_RGF_IRR_RNG_INT_BIT_SHIFT)
|
||||
|
||||
/* RNG interrupt mask */
|
||||
#define CC_RNG_INT_MASK (BIT(CC_RNG_IMR_EHR_VALID_INT_MASK_BIT_SHIFT) | \
|
||||
BIT(CC_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SHIFT) | \
|
||||
BIT(CC_RNG_IMR_CRNGT_ERR_INT_MASK_BIT_SHIFT) | \
|
||||
BIT(CC_RNG_IMR_VN_ERR_INT_MASK_BIT_SHIFT) | \
|
||||
BIT(CC_RNG_IMR_WATCHDOG_INT_MASK_BIT_SHIFT))
|
||||
|
||||
// --------------------------------------
|
||||
// BLOCK: RNG
|
||||
// --------------------------------------
|
||||
#define CC_RNG_IMR_REG_OFFSET 0x0100UL
|
||||
#define CC_RNG_IMR_EHR_VALID_INT_MASK_BIT_SHIFT 0x0UL
|
||||
#define CC_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SHIFT 0x1UL
|
||||
#define CC_RNG_IMR_CRNGT_ERR_INT_MASK_BIT_SHIFT 0x2UL
|
||||
#define CC_RNG_IMR_VN_ERR_INT_MASK_BIT_SHIFT 0x3UL
|
||||
#define CC_RNG_IMR_WATCHDOG_INT_MASK_BIT_SHIFT 0x4UL
|
||||
#define CC_RNG_ISR_REG_OFFSET 0x0104UL
|
||||
#define CC_RNG_ISR_EHR_VALID_BIT_SHIFT 0x0UL
|
||||
#define CC_RNG_ISR_EHR_VALID_BIT_SIZE 0x1UL
|
||||
#define CC_RNG_ISR_AUTOCORR_ERR_BIT_SHIFT 0x1UL
|
||||
#define CC_RNG_ISR_AUTOCORR_ERR_BIT_SIZE 0x1UL
|
||||
#define CC_RNG_ISR_CRNGT_ERR_BIT_SHIFT 0x2UL
|
||||
#define CC_RNG_ISR_CRNGT_ERR_BIT_SIZE 0x1UL
|
||||
#define CC_RNG_ISR_WATCHDOG_BIT_SHIFT 0x4UL
|
||||
#define CC_RNG_ISR_WATCHDOG_BIT_SIZE 0x1UL
|
||||
#define CC_RNG_ICR_REG_OFFSET 0x0108UL
|
||||
#define CC_TRNG_CONFIG_REG_OFFSET 0x010CUL
|
||||
#define CC_EHR_DATA_0_REG_OFFSET 0x0114UL
|
||||
#define CC_RND_SOURCE_ENABLE_REG_OFFSET 0x012CUL
|
||||
#define CC_SAMPLE_CNT1_REG_OFFSET 0x0130UL
|
||||
#define CC_TRNG_DEBUG_CONTROL_REG_OFFSET 0x0138UL
|
||||
#define CC_RNG_SW_RESET_REG_OFFSET 0x0140UL
|
||||
#define CC_RNG_CLK_ENABLE_REG_OFFSET 0x01C4UL
|
||||
#define CC_RNG_DMA_ENABLE_REG_OFFSET 0x01C8UL
|
||||
#define CC_RNG_WATCHDOG_VAL_REG_OFFSET 0x01D8UL
|
||||
// --------------------------------------
|
||||
// BLOCK: SEC_HOST_RGF
|
||||
// --------------------------------------
|
||||
#define CC_HOST_RGF_IRR_REG_OFFSET 0x0A00UL
|
||||
#define CC_HOST_RGF_IRR_RNG_INT_BIT_SHIFT 0xAUL
|
||||
#define CC_HOST_RGF_IMR_REG_OFFSET 0x0A04UL
|
||||
#define CC_HOST_RGF_ICR_REG_OFFSET 0x0A08UL
|
||||
|
||||
#define CC_HOST_POWER_DOWN_EN_REG_OFFSET 0x0A78UL
|
||||
|
||||
// --------------------------------------
|
||||
// BLOCK: NVM
|
||||
// --------------------------------------
|
||||
#define CC_NVM_IS_IDLE_REG_OFFSET 0x0F10UL
|
||||
#define CC_NVM_IS_IDLE_VALUE_BIT_SHIFT 0x0UL
|
||||
#define CC_NVM_IS_IDLE_VALUE_BIT_SIZE 0x1UL
|
||||
Loading…
Reference in New Issue