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Merge branch 'hns3-next' 

Huazhong Tan says:

====================
code optimizations & bugfixes for HNS3 driver

This patchset includes bugfixes and code optimizations for the HNS3
ethernet controller driver

Change log:
V1->V2: fixes comment from Eric Dumazet
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2019-01-23 11:13:02 -08:00
parent 16e8292092 d3ad430ac5
commit a56d7b95be
12 changed files with 251 additions and 73 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/net/ethernet/hisilicon/hns3/hnae3.h
View File

@ -433,7 +433,8 @@ struct hnae3_ae_ops {
struct ethtool_channels *ch);
void (*get_tqps_and_rss_info)(struct hnae3_handle *h,
u16 *alloc_tqps, u16 *max_rss_size);
int (*set_channels)(struct hnae3_handle *handle, u32 new_tqps_num);
int (*set_channels)(struct hnae3_handle *handle, u32 new_tqps_num,
bool rxfh_configured);
void (*get_flowctrl_adv)(struct hnae3_handle *handle,
u32 *flowctrl_adv);
int (*set_led_id)(struct hnae3_handle *handle,

44
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
View File

@ -1399,7 +1399,12 @@ static void hns3_nic_get_stats64(struct net_device *netdev,
int queue_num = priv->ae_handle->kinfo.num_tqps;
struct hnae3_handle *handle = priv->ae_handle;
struct hns3_enet_ring *ring;
u64 rx_length_errors = 0;
u64 rx_crc_errors = 0;
u64 rx_multicast = 0;
unsigned int start;
u64 tx_errors = 0;
u64 rx_errors = 0;
unsigned int idx;
u64 tx_bytes = 0;
u64 rx_bytes = 0;
@ -1422,6 +1427,8 @@ static void hns3_nic_get_stats64(struct net_device *netdev,
tx_pkts += ring->stats.tx_pkts;
tx_drop += ring->stats.tx_busy;
tx_drop += ring->stats.sw_err_cnt;
tx_errors += ring->stats.tx_busy;
tx_errors += ring->stats.sw_err_cnt;
} while (u64_stats_fetch_retry_irq(&ring->syncp, start));
/* fetch the rx stats */
@ -1433,6 +1440,12 @@ static void hns3_nic_get_stats64(struct net_device *netdev,
rx_drop += ring->stats.non_vld_descs;
rx_drop += ring->stats.err_pkt_len;
rx_drop += ring->stats.l2_err;
rx_errors += ring->stats.non_vld_descs;
rx_errors += ring->stats.l2_err;
rx_crc_errors += ring->stats.l2_err;
rx_crc_errors += ring->stats.l3l4_csum_err;
rx_multicast += ring->stats.rx_multicast;
rx_length_errors += ring->stats.err_pkt_len;
} while (u64_stats_fetch_retry_irq(&ring->syncp, start));
}
@ -1441,15 +1454,15 @@ static void hns3_nic_get_stats64(struct net_device *netdev,
stats->rx_bytes = rx_bytes;
stats->rx_packets = rx_pkts;
stats->rx_errors = netdev->stats.rx_errors;
stats->multicast = netdev->stats.multicast;
stats->rx_length_errors = netdev->stats.rx_length_errors;
stats->rx_crc_errors = netdev->stats.rx_crc_errors;
stats->rx_errors = rx_errors;
stats->multicast = rx_multicast;
stats->rx_length_errors = rx_length_errors;
stats->rx_crc_errors = rx_crc_errors;
stats->rx_missed_errors = netdev->stats.rx_missed_errors;
stats->tx_errors = netdev->stats.tx_errors;
stats->rx_dropped = rx_drop + netdev->stats.rx_dropped;
stats->tx_dropped = tx_drop + netdev->stats.tx_dropped;
stats->tx_errors = tx_errors;
stats->rx_dropped = rx_drop;
stats->tx_dropped = tx_drop;
stats->collisions = netdev->stats.collisions;
stats->rx_over_errors = netdev->stats.rx_over_errors;
stats->rx_frame_errors = netdev->stats.rx_frame_errors;
@ -2572,6 +2585,7 @@ static int hns3_handle_rx_bd(struct hns3_enet_ring *ring,
struct sk_buff **out_skb)
{
struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
enum hns3_pkt_l2t_type l2_frame_type;
struct sk_buff *skb = ring->skb;
struct hns3_desc_cb *desc_cb;
struct hns3_desc *desc;
@ -2680,7 +2694,12 @@ static int hns3_handle_rx_bd(struct hns3_enet_ring *ring,
return -EFAULT;
}
l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
HNS3_RXD_DMAC_S);
u64_stats_update_begin(&ring->syncp);
if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
ring->stats.rx_multicast++;
ring->stats.rx_pkts++;
ring->stats.rx_bytes += skb->len;
u64_stats_update_end(&ring->syncp);
@ -3378,6 +3397,11 @@ static void hns3_fini_ring(struct hns3_enet_ring *ring)
ring->desc_cb = NULL;
ring->next_to_clean = 0;
ring->next_to_use = 0;
ring->pending_buf = 0;
if (ring->skb) {
dev_kfree_skb_any(ring->skb);
ring->skb = NULL;
}
}
static int hns3_buf_size2type(u32 buf_size)
@ -4144,6 +4168,7 @@ int hns3_set_channels(struct net_device *netdev,
{
struct hnae3_handle *h = hns3_get_handle(netdev);
struct hnae3_knic_private_info *kinfo = &h->kinfo;
bool rxfh_configured = netif_is_rxfh_configured(netdev);
u32 new_tqp_num = ch->combined_count;
u16 org_tqp_num;
int ret;
@ -4171,9 +4196,10 @@ int hns3_set_channels(struct net_device *netdev,
return ret;
org_tqp_num = h->kinfo.num_tqps;
ret = h->ae_algo->ops->set_channels(h, new_tqp_num);
ret = h->ae_algo->ops->set_channels(h, new_tqp_num, rxfh_configured);
if (ret) {
ret = h->ae_algo->ops->set_channels(h, org_tqp_num);
ret = h->ae_algo->ops->set_channels(h, org_tqp_num,
rxfh_configured);
if (ret) {
/* If revert to old tqp failed, fatal error occurred */
dev_err(&netdev->dev,

8
drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
View File

@ -202,6 +202,13 @@ enum hns3_nic_state {
#define HNS3_RING_EN_B 0
enum hns3_pkt_l2t_type {
HNS3_L2_TYPE_UNICAST,
HNS3_L2_TYPE_MULTICAST,
HNS3_L2_TYPE_BROADCAST,
HNS3_L2_TYPE_INVALID,
};
enum hns3_pkt_l3t_type {
HNS3_L3T_NONE,
HNS3_L3T_IPV6,
@ -376,6 +383,7 @@ struct ring_stats {
u64 err_bd_num;
u64 l2_err;
u64 l3l4_csum_err;
u64 rx_multicast;
};
};
};

1
drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
View File

@ -47,6 +47,7 @@ static const struct hns3_stats hns3_rxq_stats[] = {
HNS3_TQP_STAT("err_bd_num", err_bd_num),
HNS3_TQP_STAT("l2_err", l2_err),
HNS3_TQP_STAT("l3l4_csum_err", l3l4_csum_err),
HNS3_TQP_STAT("multicast", rx_multicast),
};
#define HNS3_RXQ_STATS_COUNT ARRAY_SIZE(hns3_rxq_stats)

12
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
View File

@ -170,8 +170,12 @@ static bool hclge_is_special_opcode(u16 opcode)
/* these commands have several descriptors,
* and use the first one to save opcode and return value
*/
u16 spec_opcode[3] = {HCLGE_OPC_STATS_64_BIT,
HCLGE_OPC_STATS_32_BIT, HCLGE_OPC_STATS_MAC};
u16 spec_opcode[] = {HCLGE_OPC_STATS_64_BIT,
HCLGE_OPC_STATS_32_BIT,
HCLGE_OPC_STATS_MAC,
HCLGE_OPC_STATS_MAC_ALL,
HCLGE_OPC_QUERY_32_BIT_REG,
HCLGE_OPC_QUERY_64_BIT_REG};
int i;
for (i = 0; i < ARRAY_SIZE(spec_opcode); i++) {
@ -259,6 +263,10 @@ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
if (desc_ret == HCLGE_CMD_EXEC_SUCCESS)
retval = 0;
else if (desc_ret == HCLGE_CMD_NO_AUTH)
retval = -EPERM;
else if (desc_ret == HCLGE_CMD_NOT_SUPPORTED)
retval = -EOPNOTSUPP;
else
retval = -EIO;
hw->cmq.last_status = desc_ret;

4
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
View File

@ -39,7 +39,7 @@ struct hclge_cmq_ring {
enum hclge_cmd_return_status {
HCLGE_CMD_EXEC_SUCCESS = 0,
HCLGE_CMD_NO_AUTH = 1,
HCLGE_CMD_NOT_EXEC = 2,
HCLGE_CMD_NOT_SUPPORTED = 2,
HCLGE_CMD_QUEUE_FULL = 3,
};
@ -82,6 +82,8 @@ enum hclge_opcode_type {
HCLGE_OPC_STATS_64_BIT = 0x0030,
HCLGE_OPC_STATS_32_BIT = 0x0031,
HCLGE_OPC_STATS_MAC = 0x0032,
HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033,
HCLGE_OPC_STATS_MAC_ALL = 0x0034,
HCLGE_OPC_QUERY_REG_NUM = 0x0040,
HCLGE_OPC_QUERY_32_BIT_REG = 0x0041,

19
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
View File

@ -162,15 +162,11 @@ static int hclge_map_update(struct hnae3_handle *h)
struct hclge_dev *hdev = vport->back;
int ret;
ret = hclge_tm_map_cfg(hdev);
ret = hclge_tm_schd_setup_hw(hdev);
if (ret)
return ret;
ret = hclge_tm_schd_mode_hw(hdev);
if (ret)
return ret;
ret = hclge_pause_setup_hw(hdev);
ret = hclge_pause_setup_hw(hdev, false);
if (ret)
return ret;
@ -300,6 +296,9 @@ static int hclge_ieee_setpfc(struct hnae3_handle *h, struct ieee_pfc *pfc)
hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE)
return -EINVAL;
if (pfc->pfc_en == hdev->tm_info.pfc_en)
return 0;
prio_tc = hdev->tm_info.prio_tc;
pfc_map = 0;
@ -312,12 +311,10 @@ static int hclge_ieee_setpfc(struct hnae3_handle *h, struct ieee_pfc *pfc)
}
}
if (pfc_map == hdev->tm_info.hw_pfc_map)
return 0;
hdev->tm_info.hw_pfc_map = pfc_map;
hdev->tm_info.pfc_en = pfc->pfc_en;
return hclge_pause_setup_hw(hdev);
return hclge_pause_setup_hw(hdev, false);
}
/* DCBX configuration */
@ -365,7 +362,7 @@ static int hclge_setup_tc(struct hnae3_handle *h, u8 tc, u8 *prio_tc)
hclge_tm_schd_info_update(hdev, tc);
hclge_tm_prio_tc_info_update(hdev, prio_tc);
ret = hclge_tm_init_hw(hdev);
ret = hclge_tm_init_hw(hdev, false);
if (ret)
return ret;

138
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
View File

@ -118,6 +118,12 @@ static const struct hclge_comm_stats_str g_mac_stats_string[] = {
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
{"mac_rx_mac_pause_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
{"mac_tx_control_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)},
{"mac_rx_control_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)},
{"mac_tx_pfc_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)},
{"mac_tx_pfc_pri0_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
{"mac_tx_pfc_pri1_pkt_num",
@ -134,6 +140,8 @@ static const struct hclge_comm_stats_str g_mac_stats_string[] = {
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
{"mac_tx_pfc_pri7_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
{"mac_rx_pfc_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)},
{"mac_rx_pfc_pri0_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
{"mac_rx_pfc_pri1_pkt_num",
@ -287,10 +295,9 @@ static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
},
};
static int hclge_mac_update_stats(struct hclge_dev *hdev)
static int hclge_mac_update_stats_defective(struct hclge_dev *hdev)
{
#define HCLGE_MAC_CMD_NUM 21
#define HCLGE_RTN_DATA_NUM 4
u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
@ -308,15 +315,18 @@ static int hclge_mac_update_stats(struct hclge_dev *hdev)
}
for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
/* for special opcode 0032, only the first desc has the head */
if (unlikely(i == 0)) {
desc_data = (__le64 *)(&desc[i].data[0]);
n = HCLGE_RTN_DATA_NUM - 2;
n = HCLGE_RD_FIRST_STATS_NUM;
} else {
desc_data = (__le64 *)(&desc[i]);
n = HCLGE_RTN_DATA_NUM;
n = HCLGE_RD_OTHER_STATS_NUM;
}
for (k = 0; k < n; k++) {
*data++ += le64_to_cpu(*desc_data);
*data += le64_to_cpu(*desc_data);
data++;
desc_data++;
}
}
@ -324,6 +334,83 @@ static int hclge_mac_update_stats(struct hclge_dev *hdev)
return 0;
}
static int hclge_mac_update_stats_complete(struct hclge_dev *hdev, u32 desc_num)
{
u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
struct hclge_desc *desc;
__le64 *desc_data;
u16 i, k, n;
int ret;
desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_KERNEL);
hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true);
ret = hclge_cmd_send(&hdev->hw, desc, desc_num);
if (ret) {
kfree(desc);
return ret;
}
for (i = 0; i < desc_num; i++) {
/* for special opcode 0034, only the first desc has the head */
if (i == 0) {
desc_data = (__le64 *)(&desc[i].data[0]);
n = HCLGE_RD_FIRST_STATS_NUM;
} else {
desc_data = (__le64 *)(&desc[i]);
n = HCLGE_RD_OTHER_STATS_NUM;
}
for (k = 0; k < n; k++) {
*data += le64_to_cpu(*desc_data);
data++;
desc_data++;
}
}
kfree(desc);
return 0;
}
static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *desc_num)
{
struct hclge_desc desc;
__le32 *desc_data;
u32 reg_num;
int ret;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret)
return ret;
desc_data = (__le32 *)(&desc.data[0]);
reg_num = le32_to_cpu(*desc_data);
*desc_num = 1 + ((reg_num - 3) >> 2) +
(u32)(((reg_num - 3) & 0x3) ? 1 : 0);
return 0;
}
static int hclge_mac_update_stats(struct hclge_dev *hdev)
{
u32 desc_num;
int ret;
ret = hclge_mac_query_reg_num(hdev, &desc_num);
/* The firmware supports the new statistics acquisition method */
if (!ret)
ret = hclge_mac_update_stats_complete(hdev, desc_num);
else if (ret == -EOPNOTSUPP)
ret = hclge_mac_update_stats_defective(hdev);
else
dev_err(&hdev->pdev->dev, "query mac reg num fail!\n");
return ret;
}
static int hclge_tqps_update_stats(struct hnae3_handle *handle)
{
struct hnae3_knic_private_info *kinfo = &handle->kinfo;
@ -461,26 +548,6 @@ static u8 *hclge_comm_get_strings(u32 stringset,
return (u8 *)buff;
}
static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
struct net_device_stats *net_stats)
{
net_stats->tx_dropped = 0;
net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
net_stats->rx_length_errors =
hw_stats->mac_stats.mac_rx_undersize_pkt_num;
net_stats->rx_length_errors +=
hw_stats->mac_stats.mac_rx_oversize_pkt_num;
net_stats->rx_over_errors =
hw_stats->mac_stats.mac_rx_oversize_pkt_num;
}
static void hclge_update_stats_for_all(struct hclge_dev *hdev)
{
struct hnae3_handle *handle;
@ -500,8 +567,6 @@ static void hclge_update_stats_for_all(struct hclge_dev *hdev)
if (status)
dev_err(&hdev->pdev->dev,
"Update MAC stats fail, status = %d.\n", status);
hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
}
static void hclge_update_stats(struct hnae3_handle *handle,
@ -509,7 +574,6 @@ static void hclge_update_stats(struct hnae3_handle *handle,
{
struct hclge_vport *vport = hclge_get_vport(handle);
struct hclge_dev *hdev = vport->back;
struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
int status;
if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
@ -527,8 +591,6 @@ static void hclge_update_stats(struct hnae3_handle *handle,
"Update TQPS stats fail, status = %d.\n",
status);
hclge_update_netstat(hw_stats, net_stats);
clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
}
@ -2105,7 +2167,9 @@ static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
static void hclge_update_link_status(struct hclge_dev *hdev)
{
struct hnae3_client *rclient = hdev->roce_client;
struct hnae3_client *client = hdev->nic_client;
struct hnae3_handle *rhandle;
struct hnae3_handle *handle;
int state;
int i;
@ -2117,6 +2181,10 @@ static void hclge_update_link_status(struct hclge_dev *hdev)
for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
handle = &hdev->vport[i].nic;
client->ops->link_status_change(handle, state);
rhandle = &hdev->vport[i].roce;
if (rclient && rclient->ops->link_status_change)
rclient->ops->link_status_change(rhandle,
state);
}
hdev->hw.mac.link = state;
}
@ -7447,7 +7515,7 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
return ret;
}
ret = hclge_tm_init_hw(hdev);
ret = hclge_tm_init_hw(hdev, true);
if (ret) {
dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
return ret;
@ -7537,7 +7605,8 @@ static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
*max_rss_size = hdev->rss_size_max;
}
static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num,
bool rxfh_configured)
{
struct hclge_vport *vport = hclge_get_vport(handle);
struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
@ -7576,6 +7645,10 @@ static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
if (ret)
return ret;
/* RSS indirection table has been configuared by user */
if (rxfh_configured)
goto out;
/* Reinitializes the rss indirect table according to the new RSS size */
rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
if (!rss_indir)
@ -7591,6 +7664,7 @@ static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
kfree(rss_indir);
out:
if (!ret)
dev_info(&hdev->pdev->dev,
"Channels changed, rss_size from %d to %d, tqps from %d to %d",

8
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
View File

@ -16,6 +16,9 @@
#define HCLGE_MAX_PF_NUM 8
#define HCLGE_RD_FIRST_STATS_NUM 2
#define HCLGE_RD_OTHER_STATS_NUM 4
#define HCLGE_INVALID_VPORT 0xffff
#define HCLGE_PF_CFG_BLOCK_SIZE 32
@ -322,6 +325,7 @@ struct hclge_tm_info {
struct hclge_tc_info tc_info[HNAE3_MAX_TC];
enum hclge_fc_mode fc_mode;
u8 hw_pfc_map; /* Allow for packet drop or not on this TC */
u8 pfc_en; /* PFC enabled or not for user priority */
};
struct hclge_comm_stats_str {
@ -415,6 +419,10 @@ struct hclge_mac_stats {
u64 mac_rx_fcs_err_pkt_num;
u64 mac_rx_send_app_good_pkt_num;
u64 mac_rx_send_app_bad_pkt_num;
u64 mac_tx_pfc_pause_pkt_num;
u64 mac_rx_pfc_pause_pkt_num;
u64 mac_tx_ctrl_pkt_num;
u64 mac_rx_ctrl_pkt_num;
};
#define HCLGE_STATS_TIMER_INTERVAL (60 * 5)

70
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
View File

@ -947,6 +947,36 @@ static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev)
return 0;
}
static int hclge_tm_ets_tc_dwrr_cfg(struct hclge_dev *hdev)
{
#define DEFAULT_TC_WEIGHT 1
#define DEFAULT_TC_OFFSET 14
struct hclge_ets_tc_weight_cmd *ets_weight;
struct hclge_desc desc;
int i;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ETS_TC_WEIGHT, false);
ets_weight = (struct hclge_ets_tc_weight_cmd *)desc.data;
for (i = 0; i < HNAE3_MAX_TC; i++) {
struct hclge_pg_info *pg_info;
ets_weight->tc_weight[i] = DEFAULT_TC_WEIGHT;
if (!(hdev->hw_tc_map & BIT(i)))
continue;
pg_info =
&hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid];
ets_weight->tc_weight[i] = pg_info->tc_dwrr[i];
}
ets_weight->weight_offset = DEFAULT_TC_OFFSET;
return hclge_cmd_send(&hdev->hw, &desc, 1);
}
static int hclge_tm_pri_vnet_base_dwrr_pri_cfg(struct hclge_vport *vport)
{
struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
@ -996,6 +1026,19 @@ static int hclge_tm_pri_dwrr_cfg(struct hclge_dev *hdev)
ret = hclge_tm_pri_tc_base_dwrr_cfg(hdev);
if (ret)
return ret;
if (!hnae3_dev_dcb_supported(hdev))
return 0;
ret = hclge_tm_ets_tc_dwrr_cfg(hdev);
if (ret == -EOPNOTSUPP) {
dev_warn(&hdev->pdev->dev,
"fw %08x does't support ets tc weight cmd\n",
hdev->fw_version);
ret = 0;
}
return ret;
} else {
ret = hclge_tm_pri_vnet_base_dwrr_cfg(hdev);
if (ret)
@ -1005,7 +1048,7 @@ static int hclge_tm_pri_dwrr_cfg(struct hclge_dev *hdev)
return 0;
}
int hclge_tm_map_cfg(struct hclge_dev *hdev)
static int hclge_tm_map_cfg(struct hclge_dev *hdev)
{
int ret;
@ -1120,7 +1163,7 @@ static int hclge_tm_lvl34_schd_mode_cfg(struct hclge_dev *hdev)
return 0;
}
int hclge_tm_schd_mode_hw(struct hclge_dev *hdev)
static int hclge_tm_schd_mode_hw(struct hclge_dev *hdev)
{
int ret;
@ -1131,7 +1174,7 @@ int hclge_tm_schd_mode_hw(struct hclge_dev *hdev)
return hclge_tm_lvl34_schd_mode_cfg(hdev);
}
static int hclge_tm_schd_setup_hw(struct hclge_dev *hdev)
int hclge_tm_schd_setup_hw(struct hclge_dev *hdev)
{
int ret;
@ -1172,7 +1215,7 @@ static int hclge_pfc_setup_hw(struct hclge_dev *hdev)
HCLGE_RX_MAC_PAUSE_EN_MSK;
return hclge_pfc_pause_en_cfg(hdev, enable_bitmap,
hdev->tm_info.hw_pfc_map);
hdev->tm_info.pfc_en);
}
/* Each Tc has a 1024 queue sets to backpress, it divides to
@ -1255,7 +1298,7 @@ static int hclge_tm_bp_setup(struct hclge_dev *hdev)
return ret;
}
int hclge_pause_setup_hw(struct hclge_dev *hdev)
int hclge_pause_setup_hw(struct hclge_dev *hdev, bool init)
{
int ret;
@ -1271,10 +1314,15 @@ int hclge_pause_setup_hw(struct hclge_dev *hdev)
if (!hnae3_dev_dcb_supported(hdev))
return 0;
/* When MAC is GE Mode, hdev does not support pfc setting */
/* GE MAC does not support PFC, when driver is initializing and MAC
* is in GE Mode, ignore the error here, otherwise initialization
* will fail.
*/
ret = hclge_pfc_setup_hw(hdev);
if (ret)
dev_warn(&hdev->pdev->dev, "set pfc pause failed:%d\n", ret);
if (init && ret == -EOPNOTSUPP)
dev_warn(&hdev->pdev->dev, "GE MAC does not support pfc\n");
else
return ret;
return hclge_tm_bp_setup(hdev);
}
@ -1314,7 +1362,7 @@ void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc)
hclge_tm_schd_info_init(hdev);
}
int hclge_tm_init_hw(struct hclge_dev *hdev)
int hclge_tm_init_hw(struct hclge_dev *hdev, bool init)
{
int ret;
@ -1326,7 +1374,7 @@ int hclge_tm_init_hw(struct hclge_dev *hdev)
if (ret)
return ret;
ret = hclge_pause_setup_hw(hdev);
ret = hclge_pause_setup_hw(hdev, init);
if (ret)
return ret;
@ -1345,7 +1393,7 @@ int hclge_tm_schd_init(struct hclge_dev *hdev)
if (ret)
return ret;
return hclge_tm_init_hw(hdev);
return hclge_tm_init_hw(hdev, true);
}
int hclge_tm_vport_map_update(struct hclge_dev *hdev)

7
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
View File

@ -143,13 +143,12 @@ struct hclge_port_shapping_cmd {
int hclge_tm_schd_init(struct hclge_dev *hdev);
int hclge_tm_vport_map_update(struct hclge_dev *hdev);
int hclge_pause_setup_hw(struct hclge_dev *hdev);
int hclge_tm_schd_mode_hw(struct hclge_dev *hdev);
int hclge_pause_setup_hw(struct hclge_dev *hdev, bool init);
int hclge_tm_schd_setup_hw(struct hclge_dev *hdev);
void hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc);
void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc);
int hclge_tm_dwrr_cfg(struct hclge_dev *hdev);
int hclge_tm_map_cfg(struct hclge_dev *hdev);
int hclge_tm_init_hw(struct hclge_dev *hdev);
int hclge_tm_init_hw(struct hclge_dev *hdev, bool init);
int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx);
int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr);
int hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats);

10
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
View File

@ -349,16 +349,21 @@ static void hclgevf_request_link_info(struct hclgevf_dev *hdev)
void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state)
{
struct hnae3_handle *rhandle = &hdev->roce;
struct hnae3_handle *handle = &hdev->nic;
struct hnae3_client *rclient;
struct hnae3_client *client;
client = handle->client;
rclient = hdev->roce_client;
link_state =
test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state;
if (link_state != hdev->hw.mac.link) {
client->ops->link_status_change(handle, !!link_state);
if (rclient && rclient->ops->link_status_change)
rclient->ops->link_status_change(rhandle, !!link_state);
hdev->hw.mac.link = link_state;
}
}
@ -2461,7 +2466,8 @@ static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev)
struct hnae3_handle *nic = &hdev->nic;
struct hnae3_knic_private_info *kinfo = &nic->kinfo;
return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
return min_t(u32, hdev->rss_size_max,
hdev->num_tqps / kinfo->num_tc);
}
/**
@ -2482,7 +2488,7 @@ static void hclgevf_get_channels(struct hnae3_handle *handle,
ch->max_combined = hclgevf_get_max_channels(hdev);
ch->other_count = 0;
ch->max_other = 0;
ch->combined_count = hdev->num_tqps;
ch->combined_count = handle->kinfo.rss_size;
}
static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle,