net: phy: Add 25G BASE-R interface mode
Add 25gbase-r phy interface mode Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -292,6 +292,12 @@ Some of the interface modes are described below:
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Note: due to legacy usage, some 10GBASE-R usage incorrectly makes
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use of this definition.
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``PHY_INTERFACE_MODE_25GBASER``
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This is the IEEE 802.3 PCS Clause 107 defined 25GBASE-R protocol.
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The PCS is identical to 10GBASE-R, i.e. 64B/66B encoded
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running 2.5 as fast, giving a fixed bit rate of 25.78125 Gbaud.
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Please refer to the IEEE standard for further information.
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``PHY_INTERFACE_MODE_100BASEX``
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This defines IEEE 802.3 Clause 24. The link operates at a fixed data
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rate of 125Mpbs using a 4B/5B encoding scheme, resulting in an underlying
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@ -112,6 +112,7 @@ extern const int phy_10gbit_features_array[1];
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* @PHY_INTERFACE_MODE_RXAUI: Reduced XAUI
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* @PHY_INTERFACE_MODE_XAUI: 10 Gigabit Attachment Unit Interface
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* @PHY_INTERFACE_MODE_10GBASER: 10G BaseR
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* @PHY_INTERFACE_MODE_25GBASER: 25G BaseR
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* @PHY_INTERFACE_MODE_USXGMII: Universal Serial 10GE MII
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* @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN
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* @PHY_INTERFACE_MODE_MAX: Book keeping
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@ -147,6 +148,7 @@ typedef enum {
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PHY_INTERFACE_MODE_XAUI,
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/* 10GBASE-R, XFI, SFI - single lane 10G Serdes */
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PHY_INTERFACE_MODE_10GBASER,
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PHY_INTERFACE_MODE_25GBASER,
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PHY_INTERFACE_MODE_USXGMII,
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/* 10GBASE-KR - with Clause 73 AN */
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PHY_INTERFACE_MODE_10GKR,
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@ -223,6 +225,8 @@ static inline const char *phy_modes(phy_interface_t interface)
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return "xaui";
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case PHY_INTERFACE_MODE_10GBASER:
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return "10gbase-r";
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case PHY_INTERFACE_MODE_25GBASER:
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return "25gbase-r";
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case PHY_INTERFACE_MODE_USXGMII:
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return "usxgmii";
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case PHY_INTERFACE_MODE_10GKR:
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