drm/radeon/cik: Fix encoding of number of banks in tiling configuration info
There are multiple valid values, not just 0 or 1. Required to properly support 2D tiling in the userspace drivers. Cc: stable@vger.kernel.org Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2845,10 +2845,8 @@ static void cik_gpu_init(struct radeon_device *rdev)
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rdev->config.cik.tile_config |= (3 << 0);
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break;
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}
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if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
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rdev->config.cik.tile_config |= 1 << 4;
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else
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rdev->config.cik.tile_config |= 0 << 4;
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rdev->config.cik.tile_config |=
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((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
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rdev->config.cik.tile_config |=
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((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
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rdev->config.cik.tile_config |=
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