ARM: 7460/1: remove asm/locks.h
Commit 64ac24e738 ("Generic semaphore
implementation") removed the last include of this header. Apparently it
was just an oversight to keep this header. It can safely be removed now.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Paul Bolle
Russell King
parent
9fa16b7755
commit
a5203c4ce6
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@ -1,274 +0,0 @@
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/*
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* arch/arm/include/asm/locks.h
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*
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* Copyright (C) 2000 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Interrupt safe locking assembler.
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*/
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#ifndef __ASM_PROC_LOCKS_H
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#define __ASM_PROC_LOCKS_H
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#if __LINUX_ARM_ARCH__ >= 6
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#define __down_op(ptr,fail) \
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({ \
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__asm__ __volatile__( \
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"@ down_op\n" \
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"1: ldrex lr, [%0]\n" \
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" sub lr, lr, %1\n" \
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" strex ip, lr, [%0]\n" \
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" teq ip, #0\n" \
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" bne 1b\n" \
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" teq lr, #0\n" \
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" movmi ip, %0\n" \
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" blmi " #fail \
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: \
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: "r" (ptr), "I" (1) \
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: "ip", "lr", "cc"); \
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smp_mb(); \
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})
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#define __down_op_ret(ptr,fail) \
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({ \
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unsigned int ret; \
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__asm__ __volatile__( \
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"@ down_op_ret\n" \
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"1: ldrex lr, [%1]\n" \
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" sub lr, lr, %2\n" \
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" strex ip, lr, [%1]\n" \
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" teq ip, #0\n" \
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" bne 1b\n" \
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" teq lr, #0\n" \
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" movmi ip, %1\n" \
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" movpl ip, #0\n" \
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" blmi " #fail "\n" \
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" mov %0, ip" \
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: "=&r" (ret) \
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: "r" (ptr), "I" (1) \
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: "ip", "lr", "cc"); \
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smp_mb(); \
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ret; \
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})
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#define __up_op(ptr,wake) \
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({ \
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smp_mb(); \
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__asm__ __volatile__( \
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"@ up_op\n" \
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"1: ldrex lr, [%0]\n" \
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" add lr, lr, %1\n" \
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" strex ip, lr, [%0]\n" \
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" teq ip, #0\n" \
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" bne 1b\n" \
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" cmp lr, #0\n" \
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" movle ip, %0\n" \
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" blle " #wake \
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: \
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: "r" (ptr), "I" (1) \
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: "ip", "lr", "cc"); \
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})
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/*
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* The value 0x01000000 supports up to 128 processors and
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* lots of processes. BIAS must be chosen such that sub'ing
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* BIAS once per CPU will result in the long remaining
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* negative.
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*/
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#define RW_LOCK_BIAS 0x01000000
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#define RW_LOCK_BIAS_STR "0x01000000"
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#define __down_op_write(ptr,fail) \
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({ \
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__asm__ __volatile__( \
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"@ down_op_write\n" \
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"1: ldrex lr, [%0]\n" \
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" sub lr, lr, %1\n" \
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" strex ip, lr, [%0]\n" \
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" teq ip, #0\n" \
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" bne 1b\n" \
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" teq lr, #0\n" \
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" movne ip, %0\n" \
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" blne " #fail \
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: \
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: "r" (ptr), "I" (RW_LOCK_BIAS) \
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: "ip", "lr", "cc"); \
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smp_mb(); \
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})
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#define __up_op_write(ptr,wake) \
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({ \
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smp_mb(); \
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__asm__ __volatile__( \
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"@ up_op_write\n" \
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"1: ldrex lr, [%0]\n" \
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" adds lr, lr, %1\n" \
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" strex ip, lr, [%0]\n" \
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" teq ip, #0\n" \
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" bne 1b\n" \
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" movcs ip, %0\n" \
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" blcs " #wake \
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: \
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: "r" (ptr), "I" (RW_LOCK_BIAS) \
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: "ip", "lr", "cc"); \
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})
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#define __down_op_read(ptr,fail) \
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__down_op(ptr, fail)
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#define __up_op_read(ptr,wake) \
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({ \
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smp_mb(); \
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__asm__ __volatile__( \
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"@ up_op_read\n" \
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"1: ldrex lr, [%0]\n" \
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" add lr, lr, %1\n" \
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" strex ip, lr, [%0]\n" \
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" teq ip, #0\n" \
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" bne 1b\n" \
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" teq lr, #0\n" \
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" moveq ip, %0\n" \
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" bleq " #wake \
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: \
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: "r" (ptr), "I" (1) \
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: "ip", "lr", "cc"); \
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})
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#else
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#define __down_op(ptr,fail) \
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({ \
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__asm__ __volatile__( \
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"@ down_op\n" \
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" mrs ip, cpsr\n" \
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" orr lr, ip, #128\n" \
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" msr cpsr_c, lr\n" \
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" ldr lr, [%0]\n" \
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" subs lr, lr, %1\n" \
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" str lr, [%0]\n" \
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" msr cpsr_c, ip\n" \
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" movmi ip, %0\n" \
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" blmi " #fail \
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: \
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: "r" (ptr), "I" (1) \
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: "ip", "lr", "cc"); \
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smp_mb(); \
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})
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#define __down_op_ret(ptr,fail) \
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({ \
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unsigned int ret; \
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__asm__ __volatile__( \
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"@ down_op_ret\n" \
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" mrs ip, cpsr\n" \
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" orr lr, ip, #128\n" \
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" msr cpsr_c, lr\n" \
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" ldr lr, [%1]\n" \
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" subs lr, lr, %2\n" \
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" str lr, [%1]\n" \
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" msr cpsr_c, ip\n" \
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" movmi ip, %1\n" \
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" movpl ip, #0\n" \
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" blmi " #fail "\n" \
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" mov %0, ip" \
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: "=&r" (ret) \
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: "r" (ptr), "I" (1) \
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: "ip", "lr", "cc"); \
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smp_mb(); \
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ret; \
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})
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#define __up_op(ptr,wake) \
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({ \
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smp_mb(); \
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__asm__ __volatile__( \
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"@ up_op\n" \
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" mrs ip, cpsr\n" \
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" orr lr, ip, #128\n" \
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" msr cpsr_c, lr\n" \
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" ldr lr, [%0]\n" \
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" adds lr, lr, %1\n" \
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" str lr, [%0]\n" \
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" msr cpsr_c, ip\n" \
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" movle ip, %0\n" \
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" blle " #wake \
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: \
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: "r" (ptr), "I" (1) \
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: "ip", "lr", "cc"); \
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})
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/*
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* The value 0x01000000 supports up to 128 processors and
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* lots of processes. BIAS must be chosen such that sub'ing
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* BIAS once per CPU will result in the long remaining
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* negative.
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*/
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#define RW_LOCK_BIAS 0x01000000
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#define RW_LOCK_BIAS_STR "0x01000000"
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#define __down_op_write(ptr,fail) \
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({ \
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__asm__ __volatile__( \
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"@ down_op_write\n" \
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" mrs ip, cpsr\n" \
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" orr lr, ip, #128\n" \
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" msr cpsr_c, lr\n" \
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" ldr lr, [%0]\n" \
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" subs lr, lr, %1\n" \
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" str lr, [%0]\n" \
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" msr cpsr_c, ip\n" \
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" movne ip, %0\n" \
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" blne " #fail \
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: \
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: "r" (ptr), "I" (RW_LOCK_BIAS) \
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: "ip", "lr", "cc"); \
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smp_mb(); \
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})
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#define __up_op_write(ptr,wake) \
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({ \
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__asm__ __volatile__( \
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"@ up_op_write\n" \
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" mrs ip, cpsr\n" \
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" orr lr, ip, #128\n" \
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" msr cpsr_c, lr\n" \
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" ldr lr, [%0]\n" \
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" adds lr, lr, %1\n" \
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" str lr, [%0]\n" \
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" msr cpsr_c, ip\n" \
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" movcs ip, %0\n" \
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" blcs " #wake \
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: \
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: "r" (ptr), "I" (RW_LOCK_BIAS) \
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: "ip", "lr", "cc"); \
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smp_mb(); \
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})
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#define __down_op_read(ptr,fail) \
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__down_op(ptr, fail)
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#define __up_op_read(ptr,wake) \
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({ \
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smp_mb(); \
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__asm__ __volatile__( \
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"@ up_op_read\n" \
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" mrs ip, cpsr\n" \
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" orr lr, ip, #128\n" \
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" msr cpsr_c, lr\n" \
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" ldr lr, [%0]\n" \
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" adds lr, lr, %1\n" \
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" str lr, [%0]\n" \
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" msr cpsr_c, ip\n" \
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" moveq ip, %0\n" \
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" bleq " #wake \
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: \
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: "r" (ptr), "I" (1) \
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: "ip", "lr", "cc"); \
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})
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#endif
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#endif
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