drm/amd/display: Fix incorrect backlight register offset for DCN
[Why] Typo in backlight refactor inctroduced wrong register offset. [How] Change DCE to DCN register map for PWRSEQ_REF_DIV Cc: stable@vger.kernel.org Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Ashley Thomas <Ashley.Thomas2@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -49,7 +49,7 @@
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#define DCN_PANEL_CNTL_REG_LIST()\
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#define DCN_PANEL_CNTL_REG_LIST()\
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DCN_PANEL_CNTL_SR(PWRSEQ_CNTL, LVTMA), \
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DCN_PANEL_CNTL_SR(PWRSEQ_CNTL, LVTMA), \
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DCN_PANEL_CNTL_SR(PWRSEQ_STATE, LVTMA), \
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DCN_PANEL_CNTL_SR(PWRSEQ_STATE, LVTMA), \
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DCE_PANEL_CNTL_SR(PWRSEQ_REF_DIV, LVTMA), \
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DCN_PANEL_CNTL_SR(PWRSEQ_REF_DIV, LVTMA), \
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SR(BL_PWM_CNTL), \
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SR(BL_PWM_CNTL), \
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SR(BL_PWM_CNTL2), \
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SR(BL_PWM_CNTL2), \
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SR(BL_PWM_PERIOD_CNTL), \
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SR(BL_PWM_PERIOD_CNTL), \
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