dt-bindings: mmc: sdhci-msm: Convert bindings to yaml
Convert Qualcomm sdhci-msm devicetree binding to YAML. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Rob Herring <robh@kernel.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Link: https://lore.kernel.org/r/20220429220833.873672-2-bhupesh.sharma@linaro.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Bhupesh Sharma
Ulf Hansson
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* Qualcomm SDHCI controller (sdhci-msm)
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This file documents differences between the core properties in mmc.txt
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and the properties used by the sdhci-msm driver.
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Required properties:
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- compatible: Should contain a SoC-specific string and a IP version string:
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version strings:
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"qcom,sdhci-msm-v4" for sdcc versions less than 5.0
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"qcom,sdhci-msm-v5" for sdcc version 5.0
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For SDCC version 5.0.0, MCI registers are removed from SDCC
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interface and some registers are moved to HC. New compatible
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string is added to support this change - "qcom,sdhci-msm-v5".
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full compatible strings with SoC and version:
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"qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"
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"qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"
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"qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"
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"qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"
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"qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"
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"qcom,msm8992-sdhci", "qcom,sdhci-msm-v4"
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"qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"
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"qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"
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"qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"
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"qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
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"qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
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"qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"
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"qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
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"qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"
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NOTE that some old device tree files may be floating around that only
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have the string "qcom,sdhci-msm-v4" without the SoC compatible string
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but doing that should be considered a deprecated practice.
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- reg: Base address and length of the register in the following order:
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- Host controller register map (required)
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- SD Core register map (required for controllers earlier than msm-v5)
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- CQE register map (Optional, CQE support is present on SDHC instance meant
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for eMMC and version v4.2 and above)
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- Inline Crypto Engine register map (optional)
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- reg-names: When CQE register map is supplied, below reg-names are required
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- "hc" for Host controller register map
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- "core" for SD core register map
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- "cqhci" for CQE register map
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- "ice" for Inline Crypto Engine register map (optional)
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- interrupts: Should contain an interrupt-specifiers for the interrupts:
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- Host controller interrupt (required)
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- pinctrl-names: Should contain only one value - "default".
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- pinctrl-0: Should specify pin control groups used for this controller.
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- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
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- clock-names: Should contain the following:
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"iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
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"core" - SDC MMC clock (MCLK) (required)
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"bus" - SDCC bus voter clock (optional)
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"xo" - TCXO clock (optional)
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"cal" - reference clock for RCLK delay calibration (optional)
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"sleep" - sleep clock for RCLK delay calibration (optional)
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"ice" - clock for Inline Crypto Engine (optional)
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- qcom,ddr-config: Certain chipsets and platforms require particular settings
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for the DDR_CONFIG register. Use this field to specify the register
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value as per the Hardware Programming Guide.
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- qcom,dll-config: Chipset and Platform specific value. Use this field to
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specify the DLL_CONFIG register value as per Hardware Programming Guide.
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Optional Properties:
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* Following bus parameters are required for interconnect bandwidth scaling:
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- interconnects: Pairs of phandles and interconnect provider specifier
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to denote the edge source and destination ports of
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the interconnect path.
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- interconnect-names: For sdhc, we have two main paths.
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1. Data path : sdhc to ddr
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2. Config path : cpu to sdhc
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For Data interconnect path the name supposed to be
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is "sdhc-ddr" and for config interconnect path it is
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"cpu-sdhc".
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Please refer to Documentation/devicetree/bindings/
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interconnect/ for more details.
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Example:
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sdhc_1: sdhci@f9824900 {
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compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
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reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
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interrupts = <0 123 0>;
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bus-width = <8>;
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non-removable;
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vmmc-supply = <&pm8941_l20>;
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vqmmc-supply = <&pm8941_s3>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>;
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clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
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clock-names = "core", "iface";
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interconnects = <&qnoc MASTER_SDCC_ID &qnoc SLAVE_DDR_ID>,
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<&qnoc MASTER_CPU_ID &qnoc SLAVE_SDCC_ID>;
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interconnect-names = "sdhc-ddr","cpu-sdhc";
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qcom,dll-config = <0x000f642c>;
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qcom,ddr-config = <0x80040868>;
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};
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sdhc_2: sdhci@f98a4900 {
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compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
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reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
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interrupts = <0 125 0>;
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bus-width = <4>;
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cd-gpios = <&msmgpio 62 0x1>;
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vmmc-supply = <&pm8941_l21>;
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vqmmc-supply = <&pm8941_l13>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>;
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clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
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clock-names = "core", "iface";
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qcom,dll-config = <0x0007642c>;
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qcom,ddr-config = <0x80040868>;
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};
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@ -0,0 +1,192 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/mmc/sdhci-msm.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Qualcomm SDHCI controller (sdhci-msm)
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maintainers:
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- Bhupesh Sharma <bhupesh.sharma@linaro.org>
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description:
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Secure Digital Host Controller Interface (SDHCI) present on
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Qualcomm SOCs supports SD/MMC/SDIO devices.
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- qcom,apq8084-sdhci
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- qcom,msm8226-sdhci
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- qcom,msm8953-sdhci
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- qcom,msm8974-sdhci
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- qcom,msm8916-sdhci
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- qcom,msm8992-sdhci
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- qcom,msm8994-sdhci
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- qcom,msm8996-sdhci
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- qcom,qcs404-sdhci
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- qcom,sc7180-sdhci
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- qcom,sc7280-sdhci
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- qcom,sdm630-sdhci
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- qcom,sdm845-sdhci
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- qcom,sdx55-sdhci
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- qcom,sm6125-sdhci
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- qcom,sm6350-sdhci
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- qcom,sm8250-sdhci
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- enum:
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- qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
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- qcom,sdhci-msm-v5 # for sdcc version 5.0
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- items:
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- const: qcom,sdhci-msm-v4 # Deprecated (only for backward compatibility)
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# for sdcc versions less than 5.0
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reg:
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minItems: 1
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items:
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- description: Host controller register map
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- description: SD Core register map
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- description: CQE register map
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- description: Inline Crypto Engine register map
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clocks:
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minItems: 3
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items:
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- description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
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- description: SDC MMC clock, MCLK
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- description: TCXO clock
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- description: clock for Inline Crypto Engine
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- description: SDCC bus voter clock
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- description: reference clock for RCLK delay calibration
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- description: sleep clock for RCLK delay calibration
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clock-names:
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minItems: 2
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items:
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- const: iface
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- const: core
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- const: xo
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- const: ice
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- const: bus
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- const: cal
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- const: sleep
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interrupts:
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maxItems: 2
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interrupt-names:
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items:
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- const: hc_irq
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- const: pwr_irq
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pinctrl-names:
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minItems: 1
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items:
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- const: default
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- const: sleep
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pinctrl-0:
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description:
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Should specify pin control groups used for this controller.
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qcom,ddr-config:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: platform specific settings for DDR_CONFIG reg.
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qcom,dll-config:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: platform specific settings for DLL_CONFIG reg.
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iommus:
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minItems: 1
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maxItems: 8
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description: |
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phandle to apps_smmu node with sid mask.
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interconnects:
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items:
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- description: data path, sdhc to ddr
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- description: config path, cpu to sdhc
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interconnect-names:
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items:
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- const: sdhc-ddr
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- const: cpu-sdhc
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power-domains:
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description: A phandle to sdhci power domain node
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maxItems: 1
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patternProperties:
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'^opp-table(-[a-z0-9]+)?$':
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if:
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properties:
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compatible:
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const: operating-points-v2
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then:
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patternProperties:
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'^opp-?[0-9]+$':
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required:
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- required-opps
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- interrupts
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additionalProperties: true
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-sm8250.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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sdhc_2: sdhci@8804000 {
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compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
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reg = <0 0x08804000 0 0x1000>;
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interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC2_AHB_CLK>,
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<&gcc GCC_SDCC2_APPS_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface", "core", "xo";
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iommus = <&apps_smmu 0x4a0 0x0>;
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qcom,dll-config = <0x0007642c>;
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qcom,ddr-config = <0x80040868>;
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power-domains = <&rpmhpd SM8250_CX>;
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operating-points-v2 = <&sdhc2_opp_table>;
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sdhc2_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-19200000 {
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opp-hz = /bits/ 64 <19200000>;
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required-opps = <&rpmhpd_opp_min_svs>;
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};
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opp-50000000 {
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opp-hz = /bits/ 64 <50000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-202000000 {
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opp-hz = /bits/ 64 <202000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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};
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};
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