x86/mtrr: Add mtrr=debug command line option
Add a new command line option "mtrr=debug" for getting debug output after building the new cache mode map. The output will include MTRR register values and the resulting map. Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Tested-by: Michael Kelley <mikelley@microsoft.com> Link: https://lore.kernel.org/r/20230502120931.20719-13-jgross@suse.com Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
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@ -3423,6 +3423,10 @@
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[HW] Make the MicroTouch USB driver use raw coordinates
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('y', default) or cooked coordinates ('n')
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mtrr=debug [X86]
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Enable printing debug information related to MTRR
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registers at boot time.
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mtrr_chunk_size=nn[KMG] [X86]
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used for mtrr cleanup. It is largest continuous chunk
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that could hold holes aka. UC entries.
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@ -41,6 +41,23 @@ struct cache_map {
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u64 fixed:1;
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};
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static bool mtrr_debug;
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static int __init mtrr_param_setup(char *str)
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{
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int rc = 0;
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if (!str)
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return -EINVAL;
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if (!strcmp(str, "debug"))
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mtrr_debug = true;
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else
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rc = -EINVAL;
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return rc;
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}
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early_param("mtrr", mtrr_param_setup);
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/*
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* CACHE_MAP_MAX is the maximum number of memory ranges in cache_map, where
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* no 2 adjacent ranges have the same cache mode (those would be merged).
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@ -515,6 +532,14 @@ void __init mtrr_build_map(void)
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pr_info("MTRR map: %u entries (%u fixed + %u variable; max %u), built from %u variable MTRRs\n",
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cache_map_n, cache_map_fixed, cache_map_n - cache_map_fixed,
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get_cache_map_size(), num_var_ranges + (mtrr_tom2 != 0));
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if (mtrr_debug) {
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for (i = 0; i < cache_map_n; i++) {
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pr_info("%3u: %016llx-%016llx %s\n", i,
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cache_map[i].start, cache_map[i].end - 1,
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mtrr_attrib_to_str(cache_map[i].type));
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}
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}
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}
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/* Copy the cache_map from __initdata memory to dynamically allocated one. */
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@ -721,8 +746,8 @@ static void __init print_fixed_last(void)
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if (!last_fixed_end)
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return;
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pr_debug(" %05X-%05X %s\n", last_fixed_start,
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last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type));
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pr_info(" %05X-%05X %s\n", last_fixed_start,
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last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type));
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last_fixed_end = 0;
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}
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@ -760,10 +785,10 @@ static void __init print_mtrr_state(void)
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unsigned int i;
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int high_width;
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pr_debug("MTRR default type: %s\n",
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mtrr_attrib_to_str(mtrr_state.def_type));
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pr_info("MTRR default type: %s\n",
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mtrr_attrib_to_str(mtrr_state.def_type));
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if (mtrr_state.have_fixed) {
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pr_debug("MTRR fixed ranges %sabled:\n",
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pr_info("MTRR fixed ranges %sabled:\n",
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((mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED) &&
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(mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED)) ?
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"en" : "dis");
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@ -778,27 +803,27 @@ static void __init print_mtrr_state(void)
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/* tail */
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print_fixed_last();
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}
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pr_debug("MTRR variable ranges %sabled:\n",
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mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED ? "en" : "dis");
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pr_info("MTRR variable ranges %sabled:\n",
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mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED ? "en" : "dis");
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high_width = (boot_cpu_data.x86_phys_bits - (32 - PAGE_SHIFT) + 3) / 4;
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for (i = 0; i < num_var_ranges; ++i) {
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if (mtrr_state.var_ranges[i].mask_lo & MTRR_PHYSMASK_V)
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pr_debug(" %u base %0*X%05X000 mask %0*X%05X000 %s\n",
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i,
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high_width,
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mtrr_state.var_ranges[i].base_hi,
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mtrr_state.var_ranges[i].base_lo >> 12,
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high_width,
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mtrr_state.var_ranges[i].mask_hi,
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mtrr_state.var_ranges[i].mask_lo >> 12,
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mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo &
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pr_info(" %u base %0*X%05X000 mask %0*X%05X000 %s\n",
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i,
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high_width,
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mtrr_state.var_ranges[i].base_hi,
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mtrr_state.var_ranges[i].base_lo >> 12,
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high_width,
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mtrr_state.var_ranges[i].mask_hi,
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mtrr_state.var_ranges[i].mask_lo >> 12,
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mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo &
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MTRR_PHYSBASE_TYPE));
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else
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pr_debug(" %u disabled\n", i);
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pr_info(" %u disabled\n", i);
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}
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if (mtrr_tom2)
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pr_debug("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20);
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pr_info("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20);
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}
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/* Grab all of the MTRR state for this CPU into *state */
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@ -833,7 +858,8 @@ bool __init get_mtrr_state(void)
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mtrr_tom2 &= 0xffffff800000ULL;
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}
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print_mtrr_state();
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if (mtrr_debug)
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print_mtrr_state();
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mtrr_state_set = 1;
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